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Intel OCPRF100 MP 9. Peripheral Bay Board (Chassis Side), 9.1Introduction, 9.2Mechanical Description, 9.2.1Board Layout, Features

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OCPRF100 MP Server System Technical Product Specification

Revision 1.0

9. Peripheral Bay Board (Chassis Side)

This chapter describes the design of the peripheral bay board (chassis side). This board, used in the OCPRF100 MP server system, is attached to the OCPRF100 MP server system chassis and provides power and signal distribution to the peripheral bay backplane and other system peripheral devices.

Features

The OCPRF100 MP server system peripheral bay board has the following features:

•Provides an interface which allows plugging of the peripheral bay into the system.

•Distributes power and signal connections from the midplane and I/O board to the floppy, IDE CD-ROM, and the peripheral bay backplane.

•Provides a common interface for an integrator's custom peripheral bay solutions.

9.1Introduction

The peripheral bay board (chassis side) provides power and signal interconnection from the mid- plane and I/O boards to the peripheral devices and the peripheral bay backplane. This board allows the single point connection of all power and signals required by the peripheral bay back- plane. The peripheral bay board (chassis side) contains no active components. Also, it does not provide or contain any field replaceable unit (FRU) information.

9.2Mechanical Description

The blind mate is the junction of the peripheral bay board (chassis side) with the peripheral bay backplane. The peripheral bay backplane meets the peripheral bay board (chassis side) at a 90- degree angle.

The blind mate consists of one 240-pin connector in between two long guide pins.

9.2.1Board Layout

Figure 9-1: Peripheral Bay Board (Chassis Side) Layout illustrates the layout of the peripheral bay board (chassis side) with the connectors.

Figure 9-2 shows the printed circuit board dimensions, mounting holes, and connector place- ments.

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Contents

OCPRF100 MP Server System Technical Product Specification Revision History Disclaimers OPRF100 MP Board Set OCPRF100 MP Server System Table of Contents Power Supply System Software Page Front Panel Appendix A: Glossary Appendix B: References 1. Introduction Page 2. Server System Chassis and Assemblies 2.1Front Panel Assembly 2.2Peripheral Bay 2.3Top Cover Assembly 2.3.1Hot-plugPCI Access Door 2.4Fan Bay Page 2.5Front Panel Board 2.6Processor Mezzanine Board 2.7Processor Retention Mechanism Air Baffle Strap 2.8Profusion® Carrier Tray Lock Bar Alignment Tabs Lock Bars Release Handle Page 2.9Midplane Assembly 2.10 I/O Carrier Page 2.11 Power Supply 2.12 OCPRF100 MP Server System Chassis 3. System Overview 3.1Introduction Page Page 3.2External Chassis Features 3.2.1Front View of Chassis Figure 3-4:Front View of Chassis with No Bezel Table 3-2:System Features – Front Page 3.2.2Rear View of Chassis 3.2.3Riser Board External I/O Connectors 3.2.4Peripheral Bay 3.2.53.5-inch User-accessibleDrive Bay 3.2.65.25-inch User-accessibleDrive Bay 3.2.73.5-inchSCSI Hot-swapDrive Bays 3.3Internal Chassis Features 3.3.1Power System Page 3.3.2Cooling System 3.3.2.3Cooling Summary 3.3.3PCI Hot-plug Hot-plugService Hot-plugDriver Adapter Drivers 3.3.3.4PCI Hot Plug Mechanical Implementation Page 3.4Server Management 3.4.1Front Panel Controller 3.4.2Baseboard Management Controller 3.4.3Hot-swapController 3.5Expansion Support 3.6Specifications 3.6.1Environmental Specifications 3.6.2Physical Specifications Table 3-8:Dimensions and Weight 4. Cables and Connectors Figure 4-1:OCPRF100 Server System Interconnect Diagram 4.1Cables 4.2Connectors 4.2.1User-accessibleI/O Connectors 4.2.2Serial Ports 4.2.3Parallel Port 4.2.4VGA Video Port 4.2.5Universal Serial Bus Interface 4.2.6ICMB Connectors 4.2.7Fan Connector 4.2.8Peripheral Bay Power Connector 4.2.9Peripheral Bay Backplane Header Page 4.2.10LED Board Connector 4.2.11SCSI Connector 4.2.12IDE Connectors 4.2.13Floppy Connectors 5. Power Supply 5.1Mechanical Requirements 5.1.1Mechanical Outline 5.1.2Fan Requirements 5.2Interface Requirements 5.2.1AC Inlet Connector 5.2.2DC Output Connector(s) 5.3Marking and Identification 5.3.1LED Labeling 5.4Internal System Marking Figure 5-3:Internal Label Figure 5-4:Service Label 5.5Electrical Requirements 5.5.1Efficiency 5.5.2AC Input Voltage Specification 5.5.3AC Input Voltage Ranges 5.5.4DC Output Specification 5.5.4.2Remote Sense 5.5.4.3Ripple and Noise 5.5.4.4Over-voltageProtection 5.5.4.5Over-currentProtection 5.5.4.6Short Circuit Protection 5.6Control Signals 5.6.1Power Supply On (Input) 5.6.2AC OK Signal (Output) 5.6.3Power Good (Output) 5.6.4Power Supply Present Indicator (Output) 5.6.5Predictive Failure Signal (Output) 5.6.6Power Supply Failure Signal (Output) 5.6.7Power Supply Kill (Input) 5.6.8Power Supply Field Replacement Unit Signals 5.6.9LED Indicators 5.7Fan Speed Control 5.8Environmental Requirements 5.8.1Physical Environment 5.8.2Thermal Protection 5.9Regulatory Agency Requirements 6. System Software 6.1System Hardware 6.1.1Processors 6.1.2Profusion® Chip Set 6.1.3I/O Subsystem 6.1.4Intelligent Platform Management Bus 6.2Industry Standards 6.2.1ACPI 6.2.2Boot Devices and Peripherals 6.2.3Management 6.2.4Configuration 6.3BIOS Setup Utility 6.3.1Main Menu Table 6-4.IDE Submenu Table 6-5:Processor Information Submenu 6.3.2Advanced Menu Table 6-8:PCI Configuration Submenu Table 6-9:PCI Mode Submenu Table 6-10:I/O Device Configuration Submenu Table 6-11:Advanced Chip Set Control Submenu 6.3.3Security Menu 6.3.4Server Menu Table 6-15:Server Management Information Submenu 6.3.5Boot Menu 6.3.6Exit Menu 6.4Flash Utility Page 7. Regulatory Specifications 7.1Safety Compliance 7.2Electromagnetic Compatibility 7.3CE Mark 7.4Electromagnetic Compatibility Notice (USA) 7.5Electromagnetic Compatibility Notices (International) 8. Peripheral Bay Backplane Board 8.1Peripheral Bay Backplane Overview 8.1.1Architectural Overview 8.1.2Placement Diagram 8.1.3Deviations from SAF-TESpecification 8.2Functional Description 8.2.1Hot-swapConnectors 8.2.2SCSI Interface 8.2.3LVD/SE Active Termination 8.2.4Power Control 8.2.5FET Short Protection 8.2.6Microcontroller 8.2.7LED Arrangement 8.2.8IPMB (I2C bus) 8.2.9Temperature Sensor 8.3Board Functions 8.3.1Reset 8.3.2Microcontroller 8.3.2.4I2C Serial Communication-SI01 8.3.2.5I2C Electrical Input/Output Specifications 8.3.2.6Noise Margin 8.3.3SCSI Controller 8.4LVDS SCSI Termination 8.4.1LVDS Termination 8.4.2Single Ended Termination 8.5Programmable Logic 8.6Memory Map 8.6.1Memory Map 8.6.1.1Flash Memory Region (0x0000 – 0x7FFF) 8.6.1.2Static RAM Region (0x8000 – 0xF7FF) 8.6.1.3Memory Mapped Registers (0xF800 – 0xFFFF) 8.6.1.3.1Drive Fault Status Region (0xF800 – 0xF8FF) 8.6.1.3.2Drive Power Enable Region (0xF900 – 0xF9FF) 8.6.2I/O Ports Table 8-4:P1 Functions Notes: 8.6.2.3P2 8.6.2.4P3 Table 8-5:P3 Functions 8.7Signal Descriptions 8.7.1Power Good Signal 8.7.2CONN_EN_L 8.7.3CONN_SDI 8.7.4CONN_SDO 8.8Electrical, Mechanical Specifications 8.8.1Connectors Figure 8-5: SCA-2Connector 80P Table 8-7: SCA-2Connector 8.8.1.3Floppy Disk Port Connection Table 8-6:Floppy Disk Connector 8.8.1.4BERG* 240-pinRight Angle 5 X 48 Connector Table 8-8:BERG* 240-PinRight Angle 5 X 48 Connector Pinout Page 8.8.1.5IDE Connector Table 8-9:IDE Connector 8.8.1.6Power Supply Connectors Table 8-10:Power Supply Connectors 9. Peripheral Bay Board (Chassis Side) 9.1Introduction 9.2Mechanical Description 9.2.1Board Layout Figure 9-1:Peripheral Bay Board (Chassis Side) Layout F i g u r e P e r p h e r i g Figure 9-2:Peripheral Bay Board (Chassis Side) Connector Layoui 10. Front Panel 10.1 Introduction 10.1.1Board Overview 10.2 Functional Description 10.2.1Microcontroller 10.2.2Memory Maps 10.2.2.1Device Maps Table 10-1:Device Maps 10.2.2.2I/O Memory Maps Table 10-2:I/O Signals and Devices Page Page 10.2.3Memory 10.2.3.3UART 10.2.3.4Serial EEPROM/Temperature Sensor Table 10-3:FRU Device Address Table 10-4:SEEPROM Programming Areas Table 10-5:FRU Information Table 10-6:I/O Signals and Devices SEEPROM Byte Map Page 10.2.4Front Panel Indicator LEDs 10.2.5Front Panel LCD 10.2.6System Power 10.2.7Reset 10.2.7.1Resetting the System 10.2.7.2Reset Inputs 10.2.7.3Reset Switch During +5 V Power Cycle 10.2.7.4Resetting the FPC 10.2.7.5Determining the System Reset State 10.2.8Speaker 10.2.9Fan Control 10.2.10 ICMB and COM2 Redirection 10.2.10.2 Receive Forced Switching The deassertion must occur whether or not it had previously been asserted 10.2.10.3 Receive Interrupt 10.2.10.4 Receive Activity Detection 10.2.10.5 ICMB Transmit Control 10.2.10.6 COM2 Transmit Control Table 10-7:Allowed Combination of States 10.2.11 Front Panel Push Buttons 10.2.12 I2C Interfaces OCPRF100 FPC Private I2C Bus Diagram Figure 10-2:Devices Not Supporting Multimaster Mode 10.2.12.2 Global I2C Bus 10.2.13 Miscellaneous Appendix A: Glossary Page Page Page Appendix B: References I2O MPS PC-100 PCI Pentium® II Xeon™ Processor PID PIIX4 Plug and Play PMM Profusion® USB VGA Wired for Management Windows Miscellaneous Index