OCPRF100 MP Server System Technical Product Specification
Revision 1.0
supply. The second is the output from an onboard Dallas DS1233* reset controller, in which RST is kept active for approximately 350 ms after the power supply has reached the selected toler- ance. These two signals are ORed to keep the board in reset. When both signals indicate that power is good, two things happen: 1) the reset signals are negated to the controllers, SCSI tar- get, and other logic; and 2) power is applied sequentially to each SCA drive connector where a drive is present. Onboard logic sequentially enables each drive’s FET drive power circuitry every 200 µsec.
8.3.2Microcontroller
The microcontroller is a Philips* P80C652FBB operating at 12 MHz. The microprocessor boots itself up via code residing in the Flash boot block. The following is a list of the microcontroller fea- tures:
•Operating frequency from 1.2 MHz to 16 MHz.
•80C51 based architecture.
•Four
•Two
•
•I2C serial interface.
•Two power control modes: idle mode,
•Operating temperature range: 0° C to +70° C.
8.3.2.1Overview
The 80C652 is a derivative of the 80C51
The 80C652 is
8.3.2.2Differences from the 80C51*
The organization of the data memory is similar to the 80C51, except that the 80C652 has an additional 128 bytes of RAM overlapped with the special function register (SFR) space. This additional RAM is addressed using indirect addressing only and is available as stack space.
8.3.2.3Special Function Registers
The 80C652 special function register space is the same as that on the 80C51, except that it contains four additional SFRs. The added registers are: S1CON, S1STA, S1DAT, and S1ADR. In addition to these, the UART special function registers SCON and SBUF have been renamed S0CON and S0BUF for clarity.
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