Intel OCPRF100 MP 10.2.10.3 Receive Interrupt, 10.2.10.2 Receive Forced Switching, 10.2.10.4 Receive Activity Detection

OCPRF100 MP Server System Technical Product Specification

Revision 1.0

10.2.10.2 Receive Forced Switching

In certain cases it is desirable to force a specific RXD (COM2 or ICMB) into the FPC’s RXD input. This section covers this forced switch capability.

To force the ICMB’s RXD signal into the FPC’s RXD input, assert the

FORCE_RXD_ICMB_LATCH and deassert the FORCE_RXD_COM2_LATCH.

To force the COM2’s RXD signal into the FPC’s RXD input, assert the FORCE_RXD_COM2_LATCH and deassert the FORCE_RXD_ICMB_LATCH.

The following (or equivalent) sequence occurs in firmware. The deassertion must occur whether or not it had previously been asserted.

Disable interrupts.

Assert desired FORCE bit.

Deassert undesired FORCE bit.

Enable interrupts.

There is no guarantee that incoming RXD streams will be coherently switched in the hardware. It is probably a good idea to discard any immediate UART receptions after a switch.

10.2.10.3 Receive Interrupt

The microcontroller interrupt number one is programmed in the PLD to be logically the same as the microcontroller’s RXD input.

10.2.10.4 Receive Activity Detection

A completely independent circuit monitors activity on the ICMB and COM2 receive inputs. This allows bus activity monitoring regardless of the state of the auto-detect switch. Note that the receive (RXD) inputs from both COM2 and ICMB are always available to the front panel, regardless of the states of the COM2_TO_FP_EN_L and the COM2_TO_SIO_EN signals.

The ICMB_ACTIVITY_LATCH becomes set when the SIN_TTL_ICMB signal becomes asserted (low). This assertion corresponds to receive activity. The latch remains asserted (set) until read by the FPC at which time the latch is cleared. The latch remains cleared until the next activity on this line is detected.

The COM2_ACTIVITY_LATCH becomes set when the SIN_TTL_COM2 signal becomes asserted (low). This assertion corresponds to receive activity. The latch remains asserted (set) until read by the FPC at which time the latch is cleared. The latch remains cleared until the next activity on this line is detected.

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