OCPRF100 MP Server System Technical Product Specification
Revision 1.0
If the boot strap processor (BSP) fails during POST, BIOS will attempt to boot the system using another processor. This feature is called fault resilient booting (FRB). For additional information on FRB, see the OPRF100 MP Board Set Technical Product Specification.
6.1.2Profusion® Chip Set
The Profusion PCIset connects the processors, memory, and four peer PCI buses. It consists of the memory access controller (MAC), data interface buffer (DIB), and PCI host bridge (PB64).
The OCPRF100 MP server system BIOS supports the following features of the chip set:
•Memory port interleaving
•Coherency filters
•Coherency rules SRAM
•Routing of memory cycles for PCI, VGA, APICs, and ROM space
•Routing of I/O cycles
•System management RAM (SMRAM)
•Bus ECC
•Memory ECC
Memory gaps from 512KB to 640KB and from 15 MB to 16 MB are not supported. The memory in these regions is treated as normal system memory;
BIOS automatically initializes system memory, the coherency filters, and the rules SRAM. It examines the
6.1.3I/O Subsystem
The OPRF100 I/O carrier provides a
The PIIX4E provides the bridge to
The SMC* Ultra I/O chip (FDC37C937APM) provides a floppy controller, parallel port, two serial ports, a keyboard port, and a mouse port. The BIOS supports four modes of the parallel port: output
70