OCPRF100 MP Server System Technical Product Specification
Revision 1.0
Table
LCD | DB4 | Output Latch # 0 | FFE0 | RW | - | 0 |
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LCD | DB5 | Output Latch # 0 | FFE0 | RW | - | 1 |
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LCD | DB6 | Output Latch # 0 | FFE0 | RW | - | 2 |
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LCD | DB7 | Output Latch # 0 | FFE0 | RW | - | 3 |
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LED | POWER_FAIL_LED_CMD | Output Latch # 0 | FFE0 | RW | - | 4 |
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LED | DRIVE_FAIL_LED_CMD | Output Latch # 0 | FFE0 | RW | - | 5 |
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System Power | POWER_GOOD_LED_CMD | Output Latch # 0 | FFE0 | RW | - | 6 |
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Reset | HARD_RESET | Output Latch # 0 | FFE0 | RW | - | 7 |
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Fan Control | FAN_LED_CMD_1 | Output Latch #1 | FFF0 | RW | - | 0 |
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Fan Control | FAN_LED_CMD_2 | Output Latch #1 | FFF0 | RW | - | 1 |
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Fan Control | FAN_LED_CMD_3 | Output Latch #1 | FFF0 | RW | - | 2 |
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Fan Control | FAN_LED_CMD_4 | Output Latch #1 | FFF0 | RW | - | 3 |
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Fan Control | FAN_LED_CMD_5 | Output Latch #1 | FFF0 | RW | - | 4 |
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Fan Control | FAN_LED_CMD_6 | Output Latch #1 | FFF0 | RW | - | 5 |
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Reserved | Reserved | Output Latch #1 | FFF0 | RW | - | 6 |
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Reserved | Reserved | Output Latch #1 | FFF0 | RW | - | 7 |
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COM2 | UART_ADDR | PLD | FFB0 | R | 27 | 0 |
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Memory | FW_BOOT_PGM_EN | PLD | FFA0 | R | 26 | 0 |
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Reset | RST_SWT_LATCH | PLD | FF90 | R | 25 | 0 |
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System Power | PWR_CNTRL_RTC_L | PLD | FF80 | R | 24 | 0 |
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Memory | FRC_UPDATE_L | PLD | FF70 | R | 23 | 0 |
| (was SPARE_JUMPER) |
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Power | POWER_CNTRL_SFC_L | PLD | FF60 | R | 22 | 0 |
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Power | POWER_GOOD | PLD | FF50 | R | 21 | 0 |
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COM2 | UART_RESET | PLD | FF30 | R | 19 | 0 |
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Memory | BOOT_PGM_EN_LATCH | PLD | FF20 | RW | 18 | 0 |
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Reset | SYS_RESET_STATE_LATCH | PLD | FF10 | RW | 17 | 0 |
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Power | PS_PWR_ON (output) | PLD | FF00 | RW | 16 | 0 |
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FP_TO_PIIX4_ | ACPI | PLD | FEF0 | RW | 15 | 0 |
PWRBTN |
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COM2/ICMB | ICMB_ACTIVITY_LATCH | PLD | FEE0 | RW | 14 | 0 |
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