Developer’s Manual March, 2003 xiii
Intel® 80200 Processor based on Intel® XScale™ Microarchitecture
Tables
2-1 Multiply with Internal Accumulate Format...................................................................................................4
2-2 MIA{<cond>} acc0, Rm, Rs.........................................................................................................................4
2-3 MIAPH{<cond>} acc0, Rm, Rs....................................................................................................................5
2-4 MIAxy{<cond>} acc0, Rm, Rs.....................................................................................................................6
2-5 Internal Accumulator Access Format............................................................................................................7
2-6 MAR{<cond>} acc0, RdLo, RdHi................................................................................................................8
2-7 MRA{<cond>} RdLo, RdHi, acc0................................................................................................................8
2-9 Second-level Descriptors for Coarse Page Table........................................................................................10
2-10 Second-level Descriptors for Fine Page Table............................................................................................10
2-8 First-level Descriptors.................................................................................................................................10
2-11 Exception Summary....................................................................................................................................12
2-12 Event Priority...............................................................................................................................................12
2-13 Intel® 80200 Processor Encoding of Fault Status for Prefetch Aborts.......................................................13
2-14 Intel® 80200 Processor Encoding of Fault Status for Data Aborts.............................................................14
3-1 Data Cache and Buffer Behavior when X = 0...............................................................................................3
3-2 Data Cache and Buffer Behavior when X = 1...............................................................................................3
3-3 Memory Operations that Impose a Fence......................................................................................................4
3-4 Valid MMU & Data/mini-data Cache Combinations....................................................................................5
7-1 MRC/MCR Format........................................................................................................................................2
7-2 LDC/STC Format..........................................................................................................................................3
7-3 CP15 Registers..............................................................................................................................................4
7-4 ID Register.....................................................................................................................................................5
7-5 Cache Type Register......................................................................................................................................5
7-6 ARM* Control Register................................................................................................................................7
7-7 Auxiliary Control Register............................................................................................................................8
7-8 Translation Table Base Register....................................................................................................................9
7-9 Domain Access Control Register..................................................................................................................9
7-10 Fault Status Register....................................................................................................................................10
7-11 Fault Address Register................................................................................................................................10
7-12 Cache Functions..........................................................................................................................................11
7-13 TLB Functions.............................................................................................................................................13
7-14 Cache Lockdown Functions........................................................................................................................14
7-15 Data Cache Lock Register...........................................................................................................................14
7-16 TLB Lockdown Functions...........................................................................................................................15
7-17 Accessing Process ID..................................................................................................................................16
7-18 Process ID Register.....................................................................................................................................16
7-19 Accessing the Debug Registers...................................................................................................................17
7-20 Coprocessor Access Register......................................................................................................................19
7-21 CP14 Registers............................................................................................................................................20
7-22 Accessing the Performance Monitoring Registers......................................................................................20
7-23 PWRMODE Register..................................................................................................................................21
7-24 Clock and Power Management....................................................................................................................21
7-25 CCLKCFG Register....................................................................................................................................21
7-26 Accessing the Debug Registers...................................................................................................................22
8-1 Reset CCLK Configuration...........................................................................................................................1
8-2 Software CCLK Configuration......................................................................................................................2
8-3 Low Power Modes.........................................................................................................................................5
8-4 PWRSTATUS[1:0] Encoding.......................................................................................................................5