Intel 80200, Processor 3.3 Interaction of the MMU, Instruction Cache, and Data Cache

Developer’s Manual March, 2003 3-5
Intel® 80200 Processor based on Intel® XScale™ Microarchitecture
Memory Management
3.3 Interaction of the MMU, Instruction Cache, and Data
Cache
The MMU, instruction cache, and data/mini-data cache may be enabled/disabled independently.
The instruction cache can be enabled with the MMU enabled or disabled. However, the data cache
can only be enabled when the MMU is enabled. Therefore only three of the four combinations of
the MMU and data/mini-data cache enables are valid. The invalid combination causes undefined
results.
Table 3-4. Valid MMU & Data/mini-data Cache Combinations
MMU Data/mini-data Cache
Off Off
On Off
On On