Intel 80200, Processor - page 14

xiv March, 2003 Developer’s Manual
Intel® 80200 Processor based on Intel® XScale™ Microarchitecture
9-1 Interrupt Control Register (CP13 register 0)................................................................................................3
9-2 Interrupt Source Register (CP13, register 4)................................................................................................4
9-3 Interrupt Steer Register (CP13, register 8)...................................................................................................5
10-1 Intel® 80200 Processor based on Intel® XScale™ Microarchitecture Bus Signals......................................3
10-2 Requests on a 64-bit Bus..............................................................................................................................4
10-3 Requests on a 32-bit Bus..............................................................................................................................5
10-4 Return Order for 8-Word Burst, 64-bit Data Bus.........................................................................................7
10-5 Return Order for 8-Word Burst, 32-bit Data Bus.........................................................................................7
11-1 BCU Response to ECC Errors......................................................................................................................3
11-2 BCUCTL (Register 0)...................................................................................................................................5
11-3 BCUMOD (Register 1).................................................................................................................................7
11-4 ELOG0, ELOG1(Registers 4, 5)..................................................................................................................9
11-5 ECAR0, ECAR1(Registers 6, 7)..................................................................................................................9
11-6 ECTST (Register 8)....................................................................................................................................10
12-1 Clock Count Register (CCNT).....................................................................................................................2
12-2 Performance Monitor Count Register (PMN0 and PMN1)..........................................................................3
12-3 Performance Monitor Control Register (CP14, register 0)...........................................................................4
12-4 Performance Monitoring Events...................................................................................................................6
12-5 Some Common Uses of the PMU.................................................................................................................7
13-1 Debug Control and Status Register (DCSR)................................................................................................3
13-2 Event Priority................................................................................................................................................6
13-3 Instruction Breakpoint Address and Control Register (IBCRx)...................................................................9
13-4 Data Breakpoint Register (DBRx)..............................................................................................................10
13-5 Data Breakpoint Controls Register (DBCON)...........................................................................................10
13-6 TX RX Control Register (TXRXCTRL)....................................................................................................12
13-7 Normal RX Handshaking...........................................................................................................................13
13-8 High-Speed Download Handshaking States...............................................................................................13
13-9 TX Handshaking.........................................................................................................................................15
13-10 TXRXCTRL Mnemonic Extensions..........................................................................................................15
13-11 TX Register.................................................................................................................................................16
13-12 RX Register................................................................................................................................................16
13-13 DEBUG Data Register Reset Values..........................................................................................................25
13-14 CP 14 Trace Buffer Register Summary......................................................................................................26
13-15 Checkpoint Register (CHKPTx).................................................................................................................26
13-16 TBREG Format...........................................................................................................................................27
13-17 Message Byte Formats................................................................................................................................28
13-18 LDIC Cache Functions...............................................................................................................................36
14-1 Minimum Interrupt Latency.........................................................................................................................1
14-2 Branch Latency Penalty................................................................................................................................2
14-3 Latency Example..........................................................................................................................................4
14-4 Branch Instruction Timings (Those predicted by the BTB).........................................................................4
14-5 Branch Instruction Timings (Those not predicted by the BTB)...................................................................5
14-6 Data Processing Instruction Timings............................................................................................................5
14-7 Multiply Instruction Timings........................................................................................................................6
14-8 Multiply Implicit Accumulate Instruction Timings......................................................................................7
14-9 Implicit Accumulator Access Instruction Timings.......................................................................................7
14-10 Saturated Data Processing Instruction Timings............................................................................................8
14-11 Status Register Access Instruction Timings.................................................................................................8
14-12 Load and Store Instruction Timings.............................................................................................................8
14-13 Load and Store Multiple Instruction Timings..............................................................................................8