Intel 80200, Processor 13.15.1.2 Placing the Handler in Memory,

13-48 March, 2003 Developer’s Manual
Intel® 80200 Processor based on Intel® XScale™ Microarchitecture
Software Debug
13.15.1.2 Placing the Handler in Memory
The debug handler is not required to be placed at a specific pre-defined address. However, there are
some limitations on where the handler can be placed due to the override vector tables and the
2-way set associative mini instruction cache.
In the override vector table, the reset vector must branch to the debug handler using:
•a direct branch, which limits the start of the handler code to within 32 MB of the reset vector,
or
•an indirect branch with a data processing instruction. The data processing instruction creates
an address using immediate operands and then branches to the target. An LDR to the PC does
not work because the debugger cannot set up data in memory before starting the debug
handler.
The 2-way set associative limitation is due to the fact that when the override default and relocated
vector tables are downloade d, they take up b oth ways of Set 0 (w/ addresse s 0x0 and 0xffff00 00).
Therefore, debug handler code can not be downloaded to an address that maps into Set 0, otherwise
it overwrites one of the vector tables (avoid addresses w/ lower 12 bits=0).
The instruction cache 2-way set limitation is not a problem when the reset vector uses a direct
branch, since the branch offset can be adjusted accordingly. However, it makes using indirect
branches more complicated. Now, the reset vector actually needs multiple data processing
instructions to create the target address and branch to it.
One possibility is to set up vector traps on the non-reset exception vectors. These vector locations
can then be used to extend the reset vector.
Another solution is to have the reset vector do a direct branch to some intermediate code. This
intermediate code can then uses several instructions to create the debug handler start address and
branch to it. This would require another line in the mini instruction cache, since the intermediate
code must also be downloaded. This method also requires that the layout of the debug handler be
well thought out to avoid the intermediate code overwriting a line of debug handler code, or vice
versa.
For the indirect branch cases, a temporary scratch register may be necessary to hold intermediate
values while computing the final target address. DBG_r13 can be used for this purpose (see Section
13.15.2.2, Debug Handler Restrictions for restrictions on DBG_r13 usage).