Intel 80200, Processor 10.3 Examples

10-14 March, 2003 Developer’s Manual
Intel® 80200 Processor based on Intel® XScale™ Microarchitecture
External Bus
10.3 Examples
All examples assume a 64-bit bus, in a little endian system.
10.3.1 Simple Read Word
In Figure10-4, a read request for one word at address 0x240 is issued at time 10 ns. ADS# is
asserted low at that clock edge, 0x240 is driven on A, W/R# is driven low to indicate a read
request, and 0x2 is driven onto the Len bus to indicate that the access if for four bytes. Some time
later (four clocks in this case), DValid is asserted to indicate the next sequential data cycle is
occurring. Two clock edges later the data word from 0x240 is driven onto D[31:0]. The other half
of D can be any value. The ECC or Parity bits associated with the data are driven onto DCB at the
same time as the data.
Figure 10-4. Basic Read Timing
Rd Req
0x0
Data
0x240
0
1
0
0ns 25ns 50ns 75n
MCLK
ADS#/LEN[2]
Lock/LEN[1]
W/R#/LEN[0]
A
DValid
CWF
D
BE#
DCB
Abort