Developer’s Manual March, 2003 vii
Intel® 80200 Processor based on Intel® XScale™ Microarchitecture
12.5.3 Instruction Fetch Latency Mode................................................................ ...................8
12.5.4 Data/Bus Request Buffer Full Mode ............................................................................ 9
12.5.5 Stall/Writeback Statistics ............................................................................................. 9
12.5.6 Instruction TLB Efficiency Mode ................................................................................ 10
12.5.7 Data TLB Efficiency Mode ......................................................................................... 10
12.6 Multiple Performance Monitoring Run Statistics .........................................................................1 1
12.7 Examples......................................................... ....................................................................... ....12
13 Software Debug........................................................................................113.1 Definitions........................................... .......................................................................................... 1
13.2 Debug Registers........................................ ...................................................................................1
13.3 Introduction................................................ ................................................................ ...................2
13.3.1 Halt Mode .................................................................................................................... 2
13.3.2 Monitor Mode............................................................ ...................................................2
13.4 Debug Control and Status Register (DCSR) ................................................................................ 3
13.4.1 Global Enable Bit (GE) ................................................................................................ 4
13.4.2 Halt Mode Bit (H) .........................................................................................................4
13.4.3 Vector Trap Bits (TF,TI,TD,TA,TS,TU,TR) .................................................................. 5
13.4.4 Sticky Abort Bit (SA) .................................................................................................... 5
13.4.5 Method of Entry Bits (MOE)............................................ .............................................5
13.4.6 Trace Buffer Mode Bit (M) ........................................................................................... 5
13.4.7 Trace Buffer Enable Bit (E)............................................. .............................................5
13.5 Debug Exceptions...................................................................................................... ...................6
13.5.1 Halt Mode .................................................................................................................... 6
13.5.2 Monitor Mode............................................................ ...................................................8
13.6 HW Breakpoint Resources ........................................................................................................... 9
13.6.1 Instruction Breakpoints ................................................................................................ 9
13.6.2 Data Breakpoints.. ..................................................................................................... 10
13.7 Software Breakpoints................................................................................................. .................11
13.8 Transmit/Receive Control Register (TXRXCTRL) ...................................................................... 12
13.8.1 RX Register Ready Bit (RR) ......................................................................................1 3
13.8.2 Overflow Flag (OV)................... .................................................................................14
13.8.3 Download Flag (D)....................................................................... ..............................14
13.8.4 TX Register Ready Bit (TR)................... ....................................................................15
13.8.5 Conditional Execution Using TXRXCTRL....................... ...........................................15
13.9 Transmit Register (TX) ............................................................................................................... 16
13.10 Receive Register (RX)............................... .................................................................................16
13.11 Debug JTAG Access .................................................................................................................. 17
13.11.1 SELDCSR JTAG Command.................. ....................................................................17
13.11.2 SELDCSR JTAG Register ......................................................................................... 18
13.11.2.1 DBG.HLD_RST....................................................................................... 19
13.11.2.2 DBG.BRK................................................................................................ 20
13.11.2.3 DBG.DCSR...................................................................... .......................20
13.11.3 DBGTX JTAG Command................................................................................. ..........20
13.11.4 DBGTX JTAG Register................................................... ...........................................21
13.11.5 DBGRX JTAG Command .......................................................................................... 21
13.11.6 DBGRX JTAG Register ............................................................................................. 22
13.11.6.1 RX Write Logic....................................................................... .................23
13.11.6.2 DBGRX Data Register........................... .................................................24
13.11.6.3 DBG.RR........................................................................... .......................24