Intel 80200, Processor 12.5.6 Instruction TLB Efficiency Mode, 12.5.7 Data TLB Efficiency Mode

12-10 March, 2003 Developer’s Manual
Intel® 80200 Processor based on Intel® XScale™ Microarchitecture
Performance Monitoring
PMN1 counts the number of writeback operations emitted by the data cache. These writebacks
occur when the data cache evicts a dirty line of data to make room for a newly requested line or as
the result of clean operation (CP15, register7).
Statistics derived from these two events:
•The percentage of total execution cycles the processor stalled because of a data dependency.
This is calculated by dividing PMN0 by CCNT, which was used to measure total execution
time. Often a compiler can reschedule code to avoid these penalties when given the right
optimization switches.
•Total number of data writeback requests to external memory can be derived solely with PMN1.
12.5.6 Instruction TLB Efficiency Mode
PMN0 totals the number of instructions that were executed, which does not include instructions
that were translated by the instruction TLB and never executed. This can happen if a branch
instruction changes the program flow; the instruction TLB may translate the next sequential
instructions after the branch, before it receives the target address of the branch.
PMN1 counts the number of instruction TLB table-walks, which occurs when there is a TLB miss.
If the instruction TLB is disabled, PMN1 does not increment.
Statistics derived from these two events:
•Instruction TLB miss-rate. This is derived by dividing PMN1 by PMN0.
•The average number of cycles it took to execute an instruction or commonly referred to as
cycles-per-instruction (CPI). CPI can be derived by dividing CCNT by PMN0, where CCNT
was used to measure total execution time.
12.5.7 Data TLB Efficiency Mode
PMN0 totals the number of data cache accesses, which includes cacheable and non-cacheable
accesses, mini-data cache access and accesses made to locations configured as data RAM.
Note that STM and LDM each count as several accesses to the data TLB depending on the number
of registers specified in the register list. LDRD registers two accesses.
PMN1 counts the number of data TLB table-walks, which occurs when there is a TLB miss. If the
data TLB is disabled, PMN1 does not increment.
The statistic derived from these two events is:
•Data TLB miss-rate. This is derived by dividing PMN1 by PMN0.