B-6 March, 2003 Developer’s Manual
Intel® 80200 Processor based on Intel® XScale™ Microarchitecture
Optimization Guide
B.2.3 Main Execution Pipeline
B.2.3.1. F1 / F2 (Instruction Fetch) Pipestages
The job of the instruction fetch stages F1 and F2 is to present the next instruction to be executed to
the ID stage. Several important functional units reside within the F1 and F2 stages, including:
•Branch Target Buffer (BTB)
•Instruction Fetch Unit (IFU)
An understanding of the BTB (See Chapter5, “Branch Target Buffer”) and IFU are important for
performance considerations. A summary of operation is provided here so that the reader may
understand its role in the F1 pipestage.
•Branch Target Buffer (BTB)
The BTB predicts the outcome of branch type instructions. Once a branch type instruction
reaches the X1 pipestage, its target address is known. If this address is different from the
address that the BTB predicted, the pipeline is flushed, execution starts at the new target
address, and the branch’s history is updated in the BTB.
•Instruction Fetch Unit (IFU)
The IFU is responsible for delivering instructions to the instruction decode (ID) pipestage.
One instruction word is delivered each cycle (if possible) to the ID. The instruction could
come from one of two sources: instruction cache or fetch buffers.
B.2.3.2. ID (Instruction Decode) Pipestage
The ID pipestage accepts an instruction word from the IFU and sends register decode information
to the RF pipestage. The ID is able to accept a new instruction word from the IFU on every clock
cycle in which there is no stall. The ID pipestage is responsible for:
•General instruction decoding (extracting the opcode, operand addresses, destination addresses
and the offset).
•Detecting undefined instructions and generating an exception.
•Dynamic expansion of complex instructions into sequence of simple instructions. Complex
instructions are defined as ones that take more than one clock cycle to issue, such as LDM,
STM, and SWP.