Intel IXF1104 manual 5.8.3Mode 0: Detailed Operation, Datasheet

IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller

Table 31. LED Interface Signal Descriptions

Pin Name	Pin #	Pin Description
		This signal is an output that provides a continuous clock synchronous to the
LED_CLK	K24	serial data stream output on the LED_DATA pin. This clock has a maximum
		speed of 720 Hz.
		The behavior of this signal remains constant in all modes of operation.
		This signal provides the data, in various formats, as a serial bit stream. The data
LED_DATA	M22	must be valid on the rising edge of the LED_CLK signal.
		In Mode 0, the data presented on this pin is TRUE (Logic 1 = High).
		In Mode 1, the data presented on this pin is INVERTED (Logic 1 = Low).
		This is an output pin, and the signal is used only in Mode 1 as the Latch enable
LED_LATCH	L22	for the shift register chain.
		This signal is not used in Mode 0, and should be left unconnected.

5.8.3Mode 0: Detailed Operation

Note: Please refer to the SGS Thompson* M5450 datasheet for device-operation information.

The operation of the LED Interface in Mode 0 is based on a 36-bit counter loop. The data for each LED is placed in turn on the serial data line and clocked out by the LED_CLK. Figure 29 shows the basic timing relationship and relative positioning in the data stream of each bit.

Figure 29 shows the 36 clocks that are output on the LED_CLK pin. The data is changed on the falling edge of the clock and is valid for almost the entire clock cycle. This ensures that the data is valid during the rising edge of the LED_CLK, which clocks the data into the M5450 device.

The actual data shown in Figure 29 consists of a chain of 36 bits, 12 of which are valid LED DATA. The 36-bit data chain is built up as follows:

Figure 29. Mode 0 Timing

1	2	3	4	25	26	27	28	29	30	31	32	33	34	35
LED_CLK
LED_DATA			1	22	23	24	25	26	27	28	29	30
LED_LATCH

Datasheet 115

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004