Intel manual 5.1.3Mixed-ModeOperation, 5.1.3.1Configuration of the IXF1104, Datasheet

IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller

5.1.3Mixed-Mode Operation

The Intel® IXF1104 gives the user the option of configuring each port for 10/100 Mbps half-duplex copper, 10/100/1000 Mbps full-duplex copper, or 1000 Mbps full-duplex fiber operation. This gives the Intel® IXF1104 the ability to support both copper and fiber operation line-side interfaces operating at the same time within a single device. (Refer to Figure 16 “Line Side Interface Multiplexed Balls” on page 57.)

The Intel® IXF1104 provides complete flexibility in line-side connectivity by offering RGMII, integrated SerDes, and GMII.

5.1.3.1Configuration of the IXF1104

The memory maps (Table 59 “MAC Control Registers ($ Port Index + Offset)” on page 155 through Table 69 “Optical Module Registers ($ 0x799 - 0x79F)” on page 161) are logically split into the following two distinct regions:

•Per-Port Registers

•Global Registers

To achieve a desired configuration for a given port, the relevant per-port registers must be configured correctly by the user. The Table 59 through Table 69 also contain registers that affect the operation of all ports, such as the SPI3 interface configuration.

See Section 8.0, “Register Set” on page 154 for a complete description of IXF1104 configuration and status registers. The Register Maps (Table 59 through Table 69) present a summary of important configuration registers.

Note: The initialization sequence provided in Section 6.1, “Change Port Mode Initialization Sequence” on page 129 must be followed for proper configuration of the IXF1104.

5.1.3.2Key Configuration Registers

The following key registers select the operational mode of a given port:

74 Datasheet

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004