Product Information, Ordering Information Sample | Intel IXF1104

IXF1104 4-Port Gigabit Ethernet Media Access Controller

10.0Product Ordering Information

Table 157 and Figure 58 provide IXF1104 product ordering information.

Table 157. Product Information

Number	Revision	Qualification	MM Number	Ship Media

HFIXF1104CE.B0 S 853714	B0	S	853714	Tray
HFIXF1104CE.B0 S 853714

Figure 58. Ordering Information – Sample

HF

IXF

1104

C

E

B0

S

E000

Build Format

E000

= Tray

E001 = Tape and reel

Qualification

Q

= Pre-production material

S

= Production material

Product Revision

xn

= 2 Alphanumeric characters

Temperature Range

A

= Ambient (0 - 55° C)

C

= Commercial (0 - 70° C)

E

= Extended (-40 - +85° C)

Internal Package Designator

L

= LQFP

P

= PLCC

N

= DIP

Q

= PQFP

H

= QFP with heat spreader

T

= TQFP

B

= BGA

C

= CBGA

E

= TBGA

K

= HSBGA (BGA with heat slug)

xxxx

= 3-5 Digit Alphanumeric Product Code

IXA Product Prefix

LXT

= PHY layer device

IXE

= Switching engine

IXF

= Formatting device (MAC)

IXP

= Network processor

Intel Package Designator

DJ

= LQFP

FA

= TQFP

FL

= PBGA (<1.0 mm pitch)

FW

= PBGA (1.27 mm pitch)

HB

= QFP with heat spreader

HD

= QFP with heat slug

HF

= CBGA

HG

= SOIC

S

= QFP

GC

= TBGA

N

= PLCC

Datasheet

227

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004

Image 227

Intel IXF1104 manual Product Information, Ordering Information Sample

IXF1104 specifications

The Intel IXF1104 is a cutting-edge Network Interface Controller (NIC) designed to meet the needs of high-speed communication in modern networking environments. As the demand for bandwidth-intensive applications continues to grow, Intel's IXF1104 is engineered to deliver exceptional performance, reliability, and scalability, making it an ideal choice for data centers and enterprise networks.

One of the main features of the IXF1104 is its support for high-speed Ethernet connectivity, providing up to 100 Gbps throughput. This capability allows organizations to handle large amounts of data traffic efficiently, accommodating everything from cloud computing to big data analytics. The NIC utilizes advanced packet processing technology which ensures minimal latency, enhancing the overall user experience.

The IXF1104 is built on a robust architecture that integrates Intel's latest processing technologies. It incorporates a multi-core processing engine that allows for parallel processing of network packets, improving the handling of simultaneous network requests. This architecture also supports offloading features, freeing up CPU resources for other critical tasks, which optimizes system performance.

In terms of technologies, the IXF1104 supports a variety of standards including Ethernet and Fiber Channel, making it versatile across different networking environments. Its compatibility with industry-standard networking protocols ensures that it can easily integrate into existing frameworks, facilitating seamless upgrades and expansions.

Another significant characteristic of the IXF1104 is its energy efficiency. With Intel’s focus on sustainability, this NIC is designed to consume less power relative to its performance output, thereby reducing overall operational costs for organizations. It employs dynamic power management features that adjust power usage based on demand, which is especially beneficial in large-scale deployments.

Additionally, security features are woven into the IXF1104 design, protecting sensitive data from potential threats. Hardware-based security functions, including encryption capabilities and secure boot processes, ensure that the NIC can safeguard data integrity against unauthorized access.

Overall, the Intel IXF1104 stands out in the crowded NIC market by offering high-performance capabilities, energy efficiency, and robust security features. Its combination of advanced technologies and characteristics positions it as a strategic asset for modern networks, empowering organizations to achieve their connectivity and performance goals in an increasingly data-driven world.

Contents

Product Features Applications Contents 5.1 104 Applications Figures Tables 133 167 203 Description Revision History Sheet 2 Revision NumberRevision Date March 25 SerDes Driver TX Power Levels Revision Number Revision Date March 25 Sheet 4 # Description Sheet 1 Revision Date August 21 Initial external release Contents Document What You Will Find in This DocumentRelated Documents General Description Internal Architecture Intel IXF1104 552-Ball Cbga Assignments Top View Ball Assignments Ball List Tables Balls Listed in Alphabetic Order by Signal NameBall List in Alphanumeric Order by Signal Name Signal Name Ball Ledlatch GND 2CCLKLedclk Leddata RMOD0 RxlosintPtpa Rfclk AC5 TxfaultintAB5 AD6 UPXDATA8 VDD UPXDATA5 VDDUPXDATA6 VDD UPXDATA7 VDD VDD5 AC4 AC8 VDD3VDD4 VDD5 Ball List in Alphanumeric Order by Ball Location Ball Signal NameBalls Listed in Alphabetic Order by Ball Location RPRTY1 TPRTY3 TDAT9RSX TPRTY1 TDAT8 UPXDATA31 UPXDATA11 VDD VDD GNDGND UPXDATA5 VDD VDD5 UPXDATA1 UPXADD3 VDD UPXADD6VDD5 UPXADD7 VDD4 UPXADD8 AC4 VDD5 AC1GND AC2 GND AC3 COL2 IXF1104 4-Port Gigabit Ethernet Media Access Controller Naming Conventions Ball Assignments and Signal Descriptions Interface Signals Interface Signal Groups Designator Signal Description TablesSPI3 Interface Signal Descriptions Sheet 1 Signal Name Ball Type Signal Name Ball Type Standard Description SPI3 Interface Signal Descriptions Sheet 2 SPI3 Interface Signal Descriptions Sheet 3 Available SPI3 Interface Signal Descriptions Sheet 4DTPA03 Direct Transmit Packet Receive Data Bus SPI3 Interface Signal Descriptions Sheet 5Polled-PHY Transmit Packet Available SPI3 Interface Signal Descriptions Sheet 6 SPI3 Interface Signal Descriptions Sheet 7 SPI3 Interface Signal Descriptions Sheet 8 Signal Name Ball Designator Type Standard Description SerDes Interface Signal Descriptions Source Synchronous Transmit Gmii Interface Signal Descriptions Sheet 1Transmit Enable Transmit Data Receiver Reference Clock Gmii Interface Signal Descriptions Sheet 2Receive Data Carrier Sense Transmit Control Rgmii Interface Signal Descriptions Sheet 1Source Synchronous Transmit Clock Receive Control Rgmii Interface Signal Descriptions Sheet 2CPU Interface Signal Descriptions Sheet 1 CPU Interface Signal Descriptions Sheet 2 Transmit Disable Transmit Pause Control Interface Signal DescriptionsOptical Module Interface Signal Descriptions Sheet 1 Signal Name Ball Type Standard Description Designator Module Definition Interrupt Optical Module Interface Signal Descriptions Sheet 2Mdio Interface Signal Descriptions Transmitter Fault Interrupt Sysresl LED Interface Signal DescriptionsJtag Interface Signal Descriptions System Interface Signal Descriptions AC4 AC8 Power Supply Signal Descriptions Total 552 Ball Usage SummaryBall Usage Summary Type Quantity Line Side Interface Multiplexed Balls Sheet 1 Copper Mode Fiber ModeMultiplexed Ball Connections GMII/RGMII/SerDes/OMI Multiplexed Ball Connections SPI3 MPHY/SPHY Interface Sheet 1 SPI3 Signals Ball Number Comments2 SPI3 MPHY/SPHY Ball Connections Line Side Interface Multiplexed Balls Sheet 2 SPI3 MPHY/SPHY Interface Sheet 2 SPI3 Ball State During ResetInterface Ball Name Ball Reset State Comment SPI3 MPHY/SPHY Interface Sheet 3 GMII/RGMII Jtag TDOCPU LED Leddata Power-Down Sequence Power Supply SequencingPower-Up Sequence Pull-Up/Pull-Down and Unused Ball Guidelines Analog Power FilteringPower Supply Power-Up Order Time Delta to Pull-Up/Pull-Down Ball Guidelines Signal Name Ball Comments Designator Analog Power Balls Functional Descriptions Media Access Controller MAC Filtering of Receive Packets Features for Fiber and Copper ModePadding of Undersized Frames on Transmit Automatic CRC Generation Filter Vlan Packets Filter CRC Error PacketsFilter on Multicast Packet Match Filter Broadcast Packets Flow Control CRC Error DetectionCRC Errored Packets Drop Enable Behavior Illustrates the Ieee 802.3 Fifo flow control functions 2.1 802.3x Flow Control Full-Duplex Operation Packet Buffering Fifo Pause Frame Format Pause Frame Format Pause Settings Transmit Pause Control Interface Half-Duplex Operation Xoff Valid Decodes for TXPAUSEADD20Operation of TX Pause Control Interface Mixed-Mode Operation Configuration of the IXF1104Key Configuration Registers Register Name Description Address Fiber ModeOperational Mode Configuration Registers Determination of Link Establishment in Forced Mode Copper ModeDetermining If Link Is Established in Auto-Negotiation Mode Fiber Forced Mode Copper Auto-Negotiation Jumbo Packet SupportSpeed Duplex Loss-less Flow Control Rx StatisticsTX Statistics RX Fifo Packet Buffer DimensionsRmon Statistics Support TX and RX Fifo Operation TX Fifo Group 1 Statistics Rmon Additional Statistics Sheet 1 Rmon Additional Statistics Sheet 2 Conventions 8.2 IXF1104 Advantages SPI3 Interface 1.1 SPI3 RX Round Robin Data Transmission Mphy OperationMphy Logical Timing Data Path Receive Timing Transmit Timing Port Network ProcessorLine-Side Interface Mode Receive Data Transmission Sphy ModeClock Rates Parity Receive Timing Sphy Sphy Logical TimingTransmit Timing Sphy Sphy Receive Logical Timing Sphy Connection for Two IXF1104 Ports 8-Bit Interface TX SPI3 Flow Control 2.9 SPI3 Flow ControlRX SPI3 Flow Control Stpa Pre-Pending Function Gigabit Media Independent Interface Gmii Gmii Interface Signal Definition Gmii Signal Multiplexing Transmit Data Bus Gmii Interface Signal DefinitionsIXF1104 Gmii Standard Source Description Transmit Reference Clock Multiplexing of Data and Control Reduced Gigabit Media Independent Interface Rgmii Txer and Rxer Coding Description Rgmii Signal DefinitionsTiming Specifics Txer and Rxer Coding Txctl Behavior In-Band Status Mdio Control and Interface4 10/100 Mbps Functionality MDC Generation Clear When DoneMdio Address Mdio Register Descriptions MDI State Machine Single MDI Command OperationManagement Frames MDI State Functional Description FeaturesSerDes Interface Autoscan Operation Normalized DRVPWRx3 DRVPWRx2 DRVPWRx1 DRVPWRx0 Transmitter Programmable Driver-Power LevelsSerDes Driver TX Power Levels Transmitter Operational Overview Receiver Jitter Tolerance Selective Power-DownReceiver Operational Overview Receive Jitter Transmit Jitter IXF1104-to-SFP Optical Module Interface Connections Sheet 1 1 IXF1104-Supported Optical Module Interface SignalsIXF1104 SFP Signal Description Signal Names Optical Module Interface MODDEF03 Low-Speed Status Signaling InterfaceFunctional Descriptions High-Speed Serial Interface RXLOS03 TXFAULT03TXDISABLE03 Txfaultint 3.2 I2C Read Operation 3 I²C Module Configuration Interface3.1 I2C Control and Data Registers I2C Random Read Transaction 3.3 I2C Write Operation Port Protocol Operation Clock and Data Transitions 3.4 I²C Protocol Specifics I2CData Start ConditionStop Condition Acknowledge Random Read Operation Memory ResetDevice Addressing Modes of Operation LED Interface Signal DescriptionLED Interface Pin Name Pin # Pin Description Mode 0 Detailed Operation Leddata Description Mode 1 Detailed OperationMode 0 Clock Cycle to Data Bit Relationship Ledclk Cycle Ledclk Cycle Leddata Name Leddata Description Power-On, Reset, InitializationMode 1 Clock Cycle to Data Bit Relationship LED Data Decodes LEDDATA# Decodes LED Signaling BehaviorLED Behavior Fiber Mode Fiber LED Behavior Copper LED Behavior LED Behavior Copper ModeCPU Interface Write Access Read Access CPU Timing Parameters Endian Little Endian Big Endian TAP Interface JtagTAP State Machine Byte Swapper Behavior Instruction Code Description Data Register Instruction Register and Supported InstructionsInstruction Register Description Bypass Register Loopback ModesID Register Boundary Scan Register SPI3 Interface Loopback Path Line Side Interface Loopback System Interface Reference Clocks Clocks 12.1.1 CLK125 12.2 SPI3 Receive and Transmit ClocksRgmii Clocks MDC Clock LED Clock Jtag Clock12.6 I2C Clock Change Port Mode Initialization Sequence 130 Datasheet Topa Parameter Symbol Min Max Units CommentsAbsolute Maximum Ratings VDD2, VDD3 Recommended Operating Conditions DC SpecificationsParameter Symbol Min Typ Max Units Normalized Parameter Intel IXF1104 MAC DC SpecificationsSerDes Transmit Characteristics Sheet 1 Parameter Symbol Min Typ Max Units Comments Cmos I/O Cells Intel IXF1104 MAC SerDes Receive Characteristics Undershoot / Overshoot SpecificationsRgmii Electrical Characteristics SerDes Transmit Characteristics Sheet 2 IL V ILM AX V CC = M Rgmii PowerSymbol Parameter Conditions Min Max Units IH V IHM in V CC = M Receive Interface Timing SPI3 AC Timing Specifications Symbol Parameter Min Max Units SPI3 Receive Interface Signal Parameters SPI3 Transmit Interface Timing Transmit Interface Timing SPI3 Transmit Interface Signal Parameters TXC Rgmii AC Timing SpecificationSymbol Parameter Min Typ Max Unit Rgmii Interface Timing Parameters 1.1 1000 BASE-T Transmit Interface Gmii AC Timing SpecificationGmii 1000BASE-T Transmit Signal Parameters 1 1000 Base-T Operation 1.2 1000BASE-T Receive Interface Gmii 1000BASE-T Receive Signal Parameters SerDes Timing Diagram SerDes Timing Parameters SerDes AC Timing Specification MDC Low-Speed Operation Timing Mdio AC Timing SpecificationMDC High-Speed Operation Timing Mdio Timing Parameters Parameter Symbol Min Typ Max Units Test ConditionsMdio AC Timing 1 I2C Interface Timing Optical Module and I2C AC Timing SpecificationI2C AC Timing Characteristics Sheet 1 I2C AC Timing Characteristics Sheet 2 CPU Interface Write Cycle AC Timing CPU AC Timing SpecificationCPU Interface Read Cycle AC Timing Symbol Parameter Min Max CPU Interface Write Cycle AC Signal Parameters Transmit Pause Control Interface Timing Parameters Transmit Pause Control AC Timing Specification Jtag AC Timing Jtag AC Timing Parameters Jtag AC Timing Specification System Reset AC Timing System Reset AC Timing Parameters System AC Timing Specification LED Interface AC Timing Parameters LED AC Timing Specification Graphical Representation Document Structure MAC Control Registers $ Port Index + Offset Sheet 1 Register Bit Size Mode OffsetPer Port Registers Register Map MAC RX Statistics Registers $ Port Index + Offset Sheet 1 MAC Control Registers $ Port Index + Offset Sheet 2 MAC TX Statistics Registers $ Port Index + Offset MAC RX Statistics Registers $ Port Index + Offset Sheet 2 RX Fifo Registers $ 0x580 0x5BF Sheet 1 Global Status and Configuration Registers $ 0x500 0X50CRegister Bit Size Mode Address PHY Autoscan Registers $ Port Index + Offset TX Fifo Registers $ 0x600 0x63E Sheet 1 RX Fifo Registers $ 0x580 0x5BF Sheet 2 SPI3 Registers $ 0x700 0x716 Sheet 1 SPI3 Receive Configuration $0x701TX Fifo Registers $ 0x600 0x63E Sheet 2 Mdio Registers $ 0x680 Optical Module Registers $ 0x799 0x79F SPI3 Registers $ 0x700 0x716 Sheet 2SerDes Registers $ 0x780 FD FC Type $ PortIndex + MAC Control RegistersStation Address $ PortIndex +0x00 +0x01 Desired Duplex $ PortIndex + FD FC Address $ PortIndex + 0x08 + FC TX Timer Value $ PortIndex +Collision Distance $ PortIndex + Collision Threshold $ PortIndex + IPG Transmit Time $ PortIndex + 0x0C IPG Receive Time 1 $ PortIndex + 0x0AIPG Receive Time 2 $ PortIndex + 0x0B Max Frame Size Addr PortIndex + 0x0F Pause Threshold $ PortIndex + 0x0E Flush TX $ PortIndex + MAC if Mode and Rgmii Speed $ PortIndex + TX Fdfc FC Enable $ PortIndex +FC Back Pressure Length $ PortIndex + TX Hdfc Discard Unknown Control Frame $ PortIndex + RX Config Word $ PortIndex + 0x16 Sheet 1Short Runts Threshold $ PortIndex + TX Config Word $ PortIndex + 0x17 Sheet 1 RX Config Word $ PortIndex + 0x16 Sheet 2 Diverse Config Write $ PortIndex + 0x18 Sheet 1 TX Config Word $ PortIndex + 0x17 Sheet 2 RX Packet Filter Control $ PortIndex + 0x19 Sheet 1 Diverse Config Write $ PortIndex + 0x18 Sheet 2 Port Multicast Address $ PortIndex +0x1A +0x1B RX Packet Filter Control $ PortIndex + 0x19 Sheet 2 MAC RX Statistics $ PortIndex + 0x20 + 0x39 Sheet 1 MAC RX Statistics Register Overview Addr PortIndex + 0x0F on MAC RX Statistics $ PortIndex + 0x20 + 0x39 Sheet 2 Control $ PortIndex + 0x19 is set to MAC RX Statistics $ PortIndex + 0x20 + 0x39 Sheet 3 MAC RX Statistics $ PortIndex + 0x20 + 0x39 Sheet 4 MAC TX Statistics $ PortIndex +0x40 +0x58 Sheet 1 MAC TX Statistics Register Overview MAC TX Statistics $ PortIndex +0x40 +0x58 Sheet 2 MAC TX Statistics $ PortIndex +0x40 +0x58 Sheet 3 PHY Control $ Port Index + 0x60 Sheet 1 PHY Autoscan RegistersMAC TX Statistics $ PortIndex +0x40 +0x58 Sheet 4 PHY Status $ Port Index + 0x61 Sheet 1 PHY Control $ Port Index + 0x60 Sheet 2 PHY Identification 2 $ Port Index + 0x63 Sheet 1 PHY Status $ Port Index + 0x61 Sheet 2PHY Identification 1 $ Port Index + 100BASE-TX PHY Identification 2 $ Port Index + 0x63 Sheet 2Auto-Negotiation Advertisement $ Port Index + 0x64 Sheet 1 Asmdir 10BASE-T Auto-Negotiation Advertisement $ Port Index + 0x64 Sheet 2 Auto-Negotiation Expansion $ Port Index + Auto-Negotiation Next Page Transmit $ Port Index + Interface Mode $0x501 Global Status and Configuration Register OverviewPort Enable $0x500 MAC Soft Reset $0x505 Link LED Enable $0x502 LED Control $0x509 Mdio Soft Reset $0x506CPU Interface $0x508 LED Flash Rate $0x50A LED Fault Disable $0x50B Jedec ID Jtag ID $0x50C RX Fifo High Watermark Port 2 $0x582 RX Fifo Register OverviewRX Fifo High Watermark Port 0 $0x580 RX Fifo High Watermark Port 1 $0x581 RX Fifo RX Fifo High Watermark Port 3 $0x583RX Fifo Low Watermark Port 0 $0x58A RX Fifo Low Watermark Port 1 $0x58B RX Fifo Overflow Frame Drop Counter Ports 0 3 $0x594 RX Fifo Low Watermark Port 2 $0x58CRX Fifo Low Watermark Port 3 $0x58D RX Fifo Errored Frame Drop Enable $0x59F RX Fifo Port Reset $0x59E RX Fifo Overflow Event $0x5A0 Datasheet 197 RX Fifo SPI3 Loopback Enable for Ports 0 3 $0x5B2 RX Fifo Padding and CRC Strip Enable $0x5B3 RX Fifo Transfer Threshold Port 1 $0x5B9 RX Fifo Transfer Threshold Port 0 $0x5B8 RX Fifo Transfer Threshold Port 3 $0x5BB RX Fifo Transfer Threshold Port 2 $0x5BA TX Fifo High Watermark Ports 0 3 $0x600 TX Fifo Register Overview Low watermark for TX Fifo Port 2. TX Fifo Low Watermark Register Ports 0 3 $0x60A 0x60DLow watermark for TX Fifo Port 0. Low watermark for TX Fifo Port 1. MAC threshold for TX Fifo Port 2. TX Fifo MAC Threshold Register Ports 0 3 $0x614MAC threshold for TX Fifo Port 0. MAC threshold for TX Fifo Port 1. Register Description TX Fifo Overflow Event Register Description TX Fifo Out of Sequence EventRegister Description TX Fifo Underflow Event FOE1 TX Fifo Port Reset $0x620 Sheet 1Loop RX Data to TX Fifo Line-Side Loopback Ports 0 3 $0x61F FOE2 TX Fifo Overflow Frame Drop Counter Ports 0 3 $0x621 TX Fifo Port Reset $0x620 Sheet 2 TX Fifo Errored Frame Drop Counter Ports 0 3 $0x625 TX Fifo Occupancy Counter for Ports 0 3 $0x62D TX Fifo Port Drop Enable $0x63D Mdio Single Read and Write Data $0x681 Mdio Single Command $0x680Mdio Register Overview Mdio Control $0x683 Autoscan PHY Address Enable $0x682 9 SPI3 Register Overview SPI3 Transmit and Global Configuration $0x700 Sheet 1SPHY/MPHY Mode Mphy Mode SPI3 Transmit and Global Configuration $0x700 Sheet 2Sphy Mode Mphy Mode Sphy Mode SPI3 Receive Configuration $0x701 SPI3 Transmit and Global Configuration $0x700 Sheet 3 Datasheet 215 216 Datasheet Errored Frame Drop Enable $0x59F can be Sphy Mode/MPHY Mode Address Parity Error Packet Drop Counter $0x70A SerDes Register Overview TX Driver Power Level Ports 0 3 $0x784TX and RX Power-Down $0x787 RX Signal Detect Level Ports 0 3 $0x793 PortIndex + 0x10 and the Interface Mode $0x501 Clock and Interface Mode Change Enable Ports 0 3 $0x794 Optical Module Control Ports 0 3 $0x79A Optical Module Register OverviewOptical Module Status Ports 0-3 $0x799 I2C Data Ports 0 3 $0x79F I2C Control Ports 0 3 $0x79B Package Specifics for the IXF1104 Overview Package Information Cbga Package Diagram Cbga Package Side View Diagram Intel IXF1104 Example Package Marking Example Package Marking Ordering Information Sample Product Information