IXF1104
Table 147. SPI3 Receive Configuration ($0x701) (Continued)
Bit | Name | Description | Type1 | Default | |
|
|
|
|
| |
|
| SPHY Mode: |
|
| |
|
| 0 = Disables the selected SPI3 RX port. |
|
| |
11 | Rx_port_enable | 1 = Enables the selected SPI3 RX port. | R/W | 0xF | |
Port 3 | MPHY Mode: | ||||
|
|
| |||
|
| 0 = Disables the selected SPI3 RX port. |
|
| |
|
| 1 = Enables the selected SPI3 RX port. |
|
| |
|
|
|
|
| |
|
| SPHY Mode: |
|
| |
|
| 0 = Disables the selected SPI3 RX port. |
|
| |
10 | Rx_port_enable | 1 = Enables the selected SPI3 RX port. | R/W | 0xF | |
Port 2 | MPHY Mode: | ||||
|
|
| |||
|
| 0 = Disables the selected SPI3 RX port. |
|
| |
|
| 1 = Enables the selected SPI3 RX port. |
|
| |
|
|
|
|
| |
|
| SPHY Mode: |
|
| |
|
| 0 = Disables the selected SPI3 RX port. |
|
| |
9 | Rx_port_enable | 1 = Enables the selected SPI3 RX port. | R/W | 0xF | |
Port 1 | MPHY Mode: | ||||
|
|
| |||
|
| 0 = Disables the selected SPI3 RX port. |
|
| |
|
| 1 = Enables the selected SPI3 RX port. |
|
| |
|
|
|
|
| |
|
| SPHY Mode: |
|
| |
|
| 0 = Disables the selected SPI3 RX port. |
|
| |
8 | Rx_port_enable | 1 = Enables the selected SPI3 RX port. | R/W | 0xF | |
Port 0 | MPHY Mode: | ||||
|
|
| |||
|
| 0 = Disables the selected SPI3 RX port. |
|
| |
|
| 1 = Enables the selected SPI3 RX port. |
|
| |
|
|
|
|
| |
|
| SPHY Mode: |
|
| |
|
| NA. Write as 1, ignore on Read. |
|
| |
7 | Rx_core_enable | MPHY Mode: | R/W | 0x1 | |
|
| 0 = Disables the RX SPI3 core. |
|
| |
|
| 1 = Enables the RX SPI3 core. |
|
| |
|
|
|
|
| |
|
| SPHY Mode: |
|
| |
|
| NA. Write as 0, ignore on Read. |
|
| |
6:1 | IBA[5:0] | MPHY Mode: | R/W | 0x00 | |
|
| Sets the |
|
| |
|
| address during the port address selection. |
|
| |
|
|
|
|
| |
|
| SPHY Mode/MPHY Mode: |
|
| |
|
| Frames marked to be filtered (based on the |
|
| |
|
| settings in the “RX Packet Filter Control ($ |
|
| |
|
| Port_Index + 0x19)”) or frames above the “Max |
|
| |
|
| Frame Size (Addr: Port_Index + 0x0F)” that are |
|
| |
0 | RERR_enable | not dropped in the RX FIFO (see “RX FIFO | R/W | 0 | |
|
| Errored Frame Drop Enable ($0x59F)”can be |
|
| |
|
| optionally indicated with an RERR when sent out |
|
| |
|
| the SPI3 interface. |
|
| |
|
| 0 = Packets not indicated with RERR. |
|
| |
|
| 1 = Packets indicated with RERR. |
|
| |
|
|
|
|
|
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write
Datasheet | 217 |
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004