Intel IXF1104 manual 5.9CPU Interface, 5.8.6.1.2Copper LED Behavior, Datasheet

IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller

5.8.6.1.2Copper LED Behavior

Table 36. LED Behavior (Copper Mode)

Type	Status	Description
	Off	Port does not have a remote fault and “LED Control
		($0x509)” on page 189 bit is not set.
	Amber On	Port has an RGMII RXERR condition detected and
		“LED Control ($0x509)” on page 189 bit is set
Link LED
	Amber Blinking	Port has a remote fault and “LED Fault Disable
		($0x50B)” on page 190 is not set.
		“LED Control ($0x509)” on page 189 bit is set and port
	Green On	does not have an RGMII RXERR error or remote fault
		condition present.
	Off	Port is not transmitting and receiving data.
Activity LED - Green		“LED Control ($0x509)” on page 189 set: Port is
	Blinking	transmitting and/or receiving.
		“LED Control ($0x509)” on page 189 not set: Port is
		receiving data.

NOTE: Table 34 “LED_DATA# Decodes” assumes the port is enabled in the “Port Enable ($0x500)” on page 187 and the LEDs are enabled in the “LED Control ($0x509)” on page 189. If a port is not enabled, all the LEDs for that port are off. If the LEDs are not enabled, all of the LEDs are off.

5.9CPU Interface

The CPU interface block provides access to registers and statistics in the IXF1104. The interface is asynchronous externally and operates within the 125 MHz clock domain internally. The interface provides access to the following:

•Receive statistics registers

•Transmit statistics registers

•Receive FIFO registers

•Transmit FIFO registers

•Global configuration and control registers

•MAC_0 to MAC_3 registers

The CPU interface width can be configured with the two strap signals (UPX_WIDTH[1:0]) to operate as an 8-bit, 16-bit, or 32-bit bus. All internal accesses to registers are 32-bit (4, 2, or 1 data cycles respectively are required to fully access a register). When operating in 8-bit or 16-bit mode, read data for bytes [3:1] is strobed into read holding registers when byte [0] is read. Subsequent reads of bytes {1, 2, 3} in byte mode or of bytes {2,3} in 16-bit mode are supplied from the holding register independent of the upper address bits. On write accesses in 8-bit mode, the data of bytes {0, 1, 2} is similarly captured in internal write holding registers and the complete 32-bit write is committed when byte[3] is written to the IXF1104. When writing in 16-bit mode, bytes [1:0] are captured, and the double-word is committed when bytes [3:2] are written. The complete address for write is ignored (except for the write which causes the commit operation).

Datasheet 119

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004