Intel IXF1104 manual Autoscan PHY Address Enable $0x682, Mdio Control $0x683

IXF1104 4-Port Gigabit Ethernet Media Access Controller

Table 144. Autoscan PHY Address Enable ($0x682)

Bit	Name	Description		Type1	Default
Register Description: Defines valid PHY addresses. Each bit enables the corresponding
PHY address.
0 = Disable the PHY address					0x00000000
1 = Enable the PHY address
NOTE: Autoscan is only applicable for the ports in copper mode.
31:4	Reserved	Reserved		RO	0x0000000
	Autoscan PHY	Autoscan PHY address enable
3:0		0 =	Disable address	R/W	1111
	Address
		1 =	Enable address

1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write

Table 145. MDIO Control ($0x683)

Bit	Name	Description		Type1	Default
Register Description: Miscellaneous control bits.					0x00000000
31:4	Reserved	Reserved		RO	0x000
		MDIO progress. This bit reflects the status of
3	MDIO in Progress	MDIO transaction		RO	0
		0 = MDIO Single command not in progress
		1 = MDIO Single Command in progress
	MDIO in Progress	Enables the MDIO in progress bit
2		0 = Disable MDIO in progress register bit		R/W	0
	Enable
		1 = Enable MDIO in progress register bit
		Autoscan enable
1	Autoscan Enable	0 =	Disable Autoscan	R/W	0
		1 =	Enable Autoscan
		MDC speed
0	MDC Speed	0 = MDC runs at 2.5 MHz		R/W	0
		1 = MDC runs at 18 MHz

1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write

Datasheet 211

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004