Intel IXF1104 manual Contents, Datasheet

Models: IXF1104

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Contents

 

Revision Number: 006

 

Revision Date: August 21, 2003

 

(Sheet 2 of 2)

 

 

Page #

Description

 

 

140

Modified Table 53 “IPG Receive and Transmit Time Register (Addr: Port_Index + 0x0A – +

0x0C)”.

 

 

 

143

Modified Table 60 “Short Runts Threshold Register (Addr: Port_Index + 0x14)”.

 

 

143

Modified Table 61 “Discard Unknown Control Frame Register (Addr: Port_Index + 0x15)”.

 

 

143

Modified Table 62 “RX Config Word Register Bit Definition (Addr: Port_Index + 0x16)”.

 

 

145

Modified Table 64 “DiverseConfigWrite Register (Addr: Port_Index + 0x18)”.

 

 

148

Modified Table 67 “RX Statistics Registers (Addr: Port_Index + 0x20 – + 0x39)”.

 

 

163

Modified Table 82 “Microprocessor Interface Register (Addr: 0x508)”.

 

 

164

Modified Table 84 “LED Flash Rate Register (Addr: 0x50A)”.

 

 

169

Modified Table 93 “RX FIFO Errored Frame Drop Enable Register (Addr: 0x59F)”.

 

 

170

Modified Table 96 “RX FIFO Loopback Enable for Ports 0 - 3 Register (Addr: 0x5B2)”.

 

 

171

Added Table 98 “RX FIFO Jumbo Packet Size 0-3 Register (Addr: 0x5B8 – 0x5BB”.

 

 

172

Added Table 99 “RX FIFO Jumbo Packet Size Port 0 Register Bit Definitions (Addr: 0x5B8)”.

 

 

172

Added Table 100 “RX FIFO Jumbo Packet Size Port 1 Register Bit Definitions (Addr: 0x5B9)”.

 

 

172

Added Table 101 “RX FIFO Jumbo Packet Size Port 2 Register Bit Definitions (Addr: 0x5BA)”.

 

 

172

Added Table 102 “RX FIFO Jumbo Packet Size Port 3 Register Bit Definitions (Addr: 0x5BB)”.

 

 

178

Modified Table 110 “TX FIFO Number of Dropped Packets Register Ports 0-3 (Addr: 0x625 –

0x629)”.

 

 

 

177

Modified Table 108 “TX FIFO Port Reset Register (Addr: 0x620)”.

 

 

177

Modified Table 108 “TX FIFO Port Reset Register (Addr: 0x620)”.

 

 

177

Modified Table 107 “Loop RX Data to TX FIFO Register Ports 0 - 3 (Addr: 0x61F)”.

 

 

179

Added Table 111 “TX FIFO Occupancy Counter for Ports 0 - 3 Registers (Addr: 0x62D –

0x630)”.

 

 

 

180

Added Table 112 “TX FIFO Port Drop Enable Register (Addr: 0x63D)”.

 

 

181

Modified Table 114 “MDI Single Command Register (Addr: 0x680)”.

 

 

186

Added Table 122 “Tx and Rx Power-Down Register (Addr: 0x787)”.

 

 

194

Replaced Figure 53 “Intel® IXF1104 Example Package Marking”.

 

 

 

Revision 005

 

Revision Date: April 30, 2003

 

 

Page #

Description

 

 

 

Initial external release.

 

 

 

 

 

Revisions 001 through 004

 

Revision Date: April 2001 – December 2002

 

 

Page #

Description

 

 

 

Internal releases.

 

 

Datasheet

17

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004

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Intel IXF1104 manual Contents, Datasheet