Intel IXF1104 manual Datasheet

IXF1104 4-Port Gigabit Ethernet Media Access Controller

Table 54. CPU Interface Write Cycle AC Signal Parameters

Symbol	Parameter	Min	Max
Tcas	Address, chip select setup time	5 ns	–
Tcah	Address, chip select hold time	10 ns	–
Tcrr	Ready assertion to read de-assertion	10 ns	–
Tcrh	Read High width	24 ns	–
Tcdrs	Read data setup time to ready assertion	10 ns	–
Tcdrh	Read data hold time after read de-assertion	8 ns	32 ns
Tcdrd	Read data driving delay	24 ns	355 ns
Tcwl	Write assertion width	40 ns	–
Tcwh	Ready assertion to write assertion	16 ns	–
Tcdws	Write data setup to write de-assertion	10 ns	–
Tcdwh	Write data hold time after ready assertion	5 ns	–
Tcdwd	Write data sampling delay	8 ns	32 ns
Tcyd	Ready width in write cycle	24 ns	40 ns

Datasheet 149

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004