IXF1104
Table 91. RX Packet Filter Control ($ Port_Index + 0x19) (Sheet 2 of 2)
Bit | Name | Description | Type1 | Default |
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| This bit enables a Global filter on broadcast |
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| frames. |
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2 | B/Cast Drop En | 0 = All broadcast frames are passed to the SPI3 | R/W | 0 |
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| Interface. |
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| 1 = All broadcast frames are dropped.2 |
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| This bit enables a filter on multicast frames. |
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| 0 = All muticast frames are good and passed to |
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1 | M/Cast Match En | the SPI3 Interface. | R/W | 0 |
1 = Only multicast frames with a destination | ||||
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| address that matches the |
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| PortMulticastAddress are forwarded. All other |
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| muticast frames are dropped.2 |
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| This bit enables a filter on unicast frames. |
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| 0 = All unicast frames are good and are passed |
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| to the SPI3 Interface. |
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| 1 = Only unicast frames with a Destination |
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0 | U/Cast Match En2 | Address that matches the Station Address | R/W | 0 |
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| are forwarded. All other unicast frames are |
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| dropped.2 |
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| NOTE: The VLAN filter overrides the unicast filter. |
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| Therefore, a VLAN frame cannot be |
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| filtered based on the unicast address. |
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1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write
2. Used in conjunction with the “RX FIFO Errored Frame Drop Enable ($0x59F)” on page 195. This allows the frame to be dropped in the RX FIFO. Otherwise, the frame is sent out the SP3 interface and may be optionally signaled with an RERR (see bit 0 of “SPI3 Receive Configuration ($0x701)”.
Table 92. Port Multicast Address ($ Port_Index +0x1A – +0x1B)
Name | Description | Address | Type* | Default | |
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| This address compares against multicast frames |
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Port Multicast | at the receiving side if multicast filtering is | Port_Index | R/W | 0x0000000 | |
Address Low | enabled. | + 0x1A | |||
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| This register contains bits 31:0 of the address. |
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| This address compares against multicast frames |
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Port Multicast | at the receiving side if Multicast filtering is | Port_Index | R/W | 0x00000000 | |
Address High | enabled. | + 0x1B | |||
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| This register contains bits 47:32 of the address. |
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1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write
172 | Datasheet |
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
