Intel IXF1104 manual Datasheet, Receive End of Packet, bit Multi-PHYmode: REOP_0 covers, RMOD1:0

Models: IXF1104

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Receive End of Packet.

IXF1104 4-Port Gigabit Ethernet Media Access Controller

Table 3. SPI3 Interface Signal Descriptions (Sheet 8 of 8)

Signal Name

Ball

Type

Standard

Description

 

 

 

 

MPHY

SPHY

Designator

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Receive End of Packet.

 

 

 

 

 

REOP indicates the end of a packet when

REOP_0

REOP_0

C16

 

3.3 V

asserted with RVAL.

 

REOP_1

D18

Output

32-bit Multi-PHY mode: REOP_0 covers

 

REOP_2

C23

LVTTL

all 32 bits.

 

 

 

 

 

REOP_3

J19

 

 

4 x 8 Single-PHY mode: The REOP_0:3

 

 

 

 

 

 

 

 

 

 

bits correspond to the RDAT[7:0]_n

 

 

 

 

 

channels.

 

 

 

 

 

 

 

 

 

 

 

 

Receive Word Modulo:

 

 

 

 

 

32-bit Multi-PHY mode: RMOD[1:0]

 

 

 

 

 

indicates the valid bytes of data in

 

 

 

 

 

RDAT[31:0]. During transmission, RMOD is

 

 

 

 

 

always “00”, except when the last double-

 

 

 

 

 

word is transferred on RDAT[31:0].

 

 

 

 

 

RMOD[1:0] specifies the valid packet data

 

 

 

 

 

bytes on RDAT[31:0] when REOP is

 

 

 

 

 

asserted.

 

RMOD1

 

G13

 

3.3 V

RMOD[1:0]

Valid Bytes of RDAT

NA

Output

00 = 4 bytes [31:0]

RMOD0

G14

LVTTL

 

 

01 = 3 bytes [31:8]

 

 

 

 

 

 

 

 

 

 

10 = 2 bytes [31:16]

 

 

 

 

 

11 = 1 byte [31:24]

 

 

 

 

 

4 x 8 Single-PHY mode: RMOD[1:0] is not

 

 

 

 

 

required.

 

 

 

 

 

 

RMOD is considered valid only when RVAL

 

 

 

 

 

is simultaneously asserted.

 

 

 

 

 

RENB must be asserted for RMOD[1:0] to

 

 

 

 

 

be valid.

 

 

 

 

 

 

 

 

 

 

 

 

Receive Start of Transfer.

 

 

 

 

 

32-bit Multi-PHY mode: RSX indicates

 

 

 

 

 

when the in-band port address is present on

 

 

 

 

 

the RDAT bus. When RSX is High and

 

 

 

 

 

RVAL = 0, the value of RDAT[7:0] is the

RSX

NA

E13

Output

3.3 V

address of the receive FIFO to be selected.

LVTTL

Subsequent data transfers on RDAT are

 

 

 

 

 

 

 

 

 

from the FIFO specified by this in-band

 

 

 

 

 

address. Values of 0, 1, 2, and 3 select the

 

 

 

 

 

corresponding port. RSX is ignored when

 

 

 

 

 

RVAL is de-asserted.

 

 

 

 

 

4 x 8 Single-PHY mode: RSX is ignored.

 

 

 

 

 

 

 

Datasheet

45

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004

Page 45
Image 45
Intel IXF1104 manual Datasheet, Receive End of Packet, bit Multi-PHYmode: REOP_0 covers, 4 x 8 Single-PHYmode: The REOP_0:3