Intel IXF1104 manual Datasheet, Transmit Parity, bit Multi-PHYmode: TPRTY_0 is the, Transmit Error

IXF1104 4-Port Gigabit Ethernet Media Access Controller

Table 3. SPI3 Interface Signal Descriptions (Sheet 2 of 8)

Signal Name		Ball	Type	Standard	Description
MPHY	SPHY	Designator
					Transmit Parity.
					TPRTY indicates odd parity for the TDAT
					bus. TPRTY is valid only when a channel
					asserts either TENB or TSX. Odd parity is
TPRTY_0	TPRTY_0	D5			the default configuration; however, even
					parity can be selected (see Table 146 “SPI3
	TPRTY_1	G3		3.3 V
			Input		Transmit and Global Configuration
	TPRTY_2	B9		LVTTL
					($0x700)” on page 212).
	TPRTY_3	J6
					32-bit Multi-PHY mode: TPRTY_0 is the
					parity bit covering all 32 bits.
					4 x 8 Single-PHY mode: TPRTY_0:3 bits
					correspond to the respective TDAT[3:0]_n
					channels.
					Transmit Write Enable.
					TENB_0:3 asserted causes an attached
					PHY to process TDAT[n], TMOD, TSOP,
TENB_0	TENB_0	B7			TEOP and TERR signals.
	TENB_1	E2	Input	3.3 V	32-bit Multi-PHY mode: TENB_0 is the
	TENB_2	C9		LVTTL	enable bit for all 32 bits.
	TENB_3	J4			4 x 8 Single-PHY mode: TENB_0:3 bits
					correspond to the respective TDAT[3:0]_n
					channels and their associated control and
					status signals.
					Transmit Error.
					TERR indicates that there is an error in the
					current packet. TERR is valid when
TERR_0	TERR_0	A8			simultaneously asserted with TEOP and
	TERR_1	K1	Input	3.3 V	TENB.
	TERR_2	E11		LVTTL	32-bit Multi-PHY mode: TERR_0 is the bit
	TERR_3	J8			asserted for all 32 bits.
					4 x 8 Single-PHY mode: Each bit of
					TERR_0:3 corresponds to the respective
					TDAT[3:0]_n channel.
					Transmit Start-of-Packet.
					TSOP indicates the start of a packet and is
TSOP_0	TSOP_0	C7			valid when asserted simultaneously with
					TENB.
	TSOP_1	E3		3.3 V
			Input		32-bit Multi-PHY mode: TSOP_0 is the bit
	TSOP_2	C10		LVTTL
					asserted for all 32 bits.
	TSOP_3	J5
					4 x 8 Single-PHY mode: Each bit of
					TSOP_0:3 corresponds to the respective
					TDAT[3:0]_n channel.
					Transmit End-of-Packet.
					TEOP indicates the end of a packet and is
TEOP_0	TEOP_0	A7			valid when asserted simultaneously with
					TENB.
	TEOP_1	F3		3.3 V
			Input		32-bit Multi-PHY mode: TEOP_0 is the bit
	TEOP_2	E4		LVTTL
					asserted for all 32 bits.
	TEOP_3	H5
					4 x 8 Single-PHY mode: Each bit of
					TEOP_0:3 corresponds to the respective
					TDAT[3:0]_n channel.

Datasheet 39

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004