IXF1104
Table 29. SerDes Driver TX Power Levels
|
|
|
| Normalized |
|
DRVPWRx[3] | DRVPWRx[2] | DRVPWRx[1] | DRVPWRx[0] | Driver Power | Driver Power |
|
|
|
| Setting |
|
|
|
|
|
|
|
1 | 0 | 1 | 1 | 2.0 | 20 mA |
|
|
|
|
|
|
1 | 1 | 0 | 1 | 1.0 | 10 mA |
|
|
|
|
|
|
1 | 1 | 1 | 0 | 0.5 | 5 mA |
|
|
|
|
|
|
NOTE: All other values are reserved.
5.6.2.3Receiver Operational Overview
The receiver structure performs Clock and Data Recovery (CDR) on the incoming serial data stream. The quality of this operation is a dominant factor for the Bit Error Rate (BER) system performance. Feed forward and feedback controls are combined in one receiver architecture for enhanced performance. The data is
5.6.2.4Selective Power-Down
The IXF1104 offers the ability to selectively
5.6.2.5Receiver Jitter Tolerance
The SerDes receiver architecture is designed to track frequency mismatch, recover phase, and is tolerant of
104 | Datasheet |
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004