Intel IXF1104 manual

				Contents
		5.6.2.3	Receiver Operational Overview	104
		5.6.2.4	Selective Power-Down	104
		5.6.2.5	Receiver Jitter Tolerance	104
		5.6.2.6	Transmit Jitter	105
		5.6.2.7	Receive Jitter	105
5.7	Optical Module Interface			106
	5.7.1	IXF1104-Supported Optical Module Interface Signals		106
	5.7.2	Functional Descriptions		107
		5.7.2.1	High-Speed Serial Interface	107
		5.7.2.2	Low-Speed Status Signaling Interface	107
	5.7.3	I²C Module Configuration Interface		109
		5.7.3.1	I2C Control and Data Registers	109
		5.7.3.2	I2C Read Operation	109
		5.7.3.3	I2C Write Operation	110
		5.7.3.4	I²C Protocol Specifics	111
		5.7.3.5	Port Protocol Operation	111
		5.7.3.6	Clock and Data Transitions	111
5.8	LED Interface			114
	5.8.1	Modes of Operation		114
	5.8.2	LED Interface Signal Description		114
	5.8.3	Mode 0: Detailed Operation		115
	5.8.4	Mode 1: Detailed Operation		116
	5.8.5	Power-On, Reset, Initialization		117
	5.8.6	LED DATA Decodes		117
		5.8.6.1	LED Signaling Behavior	118
5.9	CPU Interface			119
	5.9.1	Functional Description		120
		5.9.1.1	Read Access	120
		5.9.1.2	Write Access	120
		5.9.1.3	CPU Timing Parameters	121
	5.9.2	Endian		121
5.10	TAP Interface (JTAG)			122
	5.10.1	TAP State Machine		122
	5.10.2	Instruction Register and Supported Instructions		123
	5.10.3	ID Register		124
	5.10.4	Boundary Scan Register		124
	5.10.5	Bypass Register		124
5.11	Loopback Modes			124
	5.11.1	SPI3 Interface Loopback		124
	5.11.2	Line Side Interface Loopback		125
5.12	Clocks	...............................................................................................................................		126
	5.12.1	System Interface Reference Clocks		126
		5.12.1.1	CLK125	127
	5.12.2	SPI3 Receive and Transmit Clocks		127
	5.12.3	RGMII Clocks		127
	5.12.4	MDC Clock		127
	5.12.5	JTAG Clock		128
	5.12.6	I2C Clock		128
	5.12.7	LED Clock		128

Datasheet 5

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004