![8.4.4PHY Autoscan Registers](/images/new-backgrounds/102532/102532359x1.webp)
IXF1104
Table 94. MAC TX Statistics ($ Port_Index +0x40 – +0x58) (Sheet 4 of 4)
Name | Description | Address | Type1 | Default | |
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TxTagged | Number of OK frames with VLAN tag. | Port_Index + | R | 0x00000000 | |
(Type field = 0x8100). | 0x55 | ||||
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| Number of frames transmitted with a | Port_Index + |
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TxCRCError | legal size but with the wrong CRC field | R | 0x00000000 | ||
0x56 | |||||
| (also called FCS field). |
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TxPauseFrames | Number of pause MAC frames | Port_Index + | R | 0x00000000 | |
transmitted. | 0x57 | ||||
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| Intentionally generates collisions to |
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| curb reception of incoming traffic due to |
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| insufficient memory available for |
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| additional frames. The port must be in |
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TxFlowControlCollisions | Port_Index + |
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enabled. | R | 0x00000000 | |||
Send | 0x58 | ||||
NOTE: To receive a correct statistic, a |
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| last frame may have to be |
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| transmitted after the last flow |
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| control collisions send. |
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| NOTE: NA - |
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1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write
8.4.4PHY Autoscan Registers
Note: These register hold the current values of the PHY registers only when Autoscan (see Section 5.5.8, “Autoscan Operation” on page 102) is enabled and the IXF1104 is configured in copper mode. These registers are not applicable in fiber mode.
Table 95. PHY Control ($ Port Index + 0x60) (Sheet 1 of 2)
Bit | Name | Description | Type1 | Default | ||
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31:16 | Reserved | Reserved | RO | 0x0000 | ||
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| PHY Soft Reset. Resets the PHY registers to their |
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| default value. |
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15 | Reset | This register bit | RO | 0 | ||
complete. | ||||||
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| 0 | = Normal Operation |
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| 1 | = PHY reset |
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14 | Loopback | 0 | = Disable loopback mode | RO | 0 | |
1 | = Enable loopback mode | |||||
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| 0.6 (Speed<1> 0.13 (Speed<0>) |
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| 00 = 10 Mbps |
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13 | Speed Selection | 01 = 100 Mbps | RO | 02 | ||
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| 10 = 1000 Mbps (manual mode not allowed) |
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| 11 = Reserved |
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1. RO = Read Only; RR = Clear on Read; W = Write; R/W = Read/Write
2. This register is ignored if
180 | Datasheet |
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004