Intel IXF1104 manual Datasheet 215

IXF1104 4-Port Gigabit Ethernet Media Access Controller

Table 147. SPI3 Receive Configuration ($0x701) (Continued)

Bit	Name	Description	Type1	Default
		SPHY Mode:
		Indicates the number of pause cycles to be
		introduced between back-to-back transfers for
25	B2B_PAUSE Port 1	port 1.	R/W	0
		0 = Zero pause cycles
		1 = Two pause cycles
		MPHY Mode:
		NA
		SPHY Mode:
		Indicates the number of pause cycles to be
		introduced between back-to-back transfers for
		port 0.
		0 = Zero pause cycles
24	B2B_PAUSE Port 0	1 = Two pause cycles	R/W	0
		MPHY Mode:
		Indicates the number of pause cycles to be
		introduced between back-to-back transfers for all
		ports.
		0 = Zero pause cycles
		1 = Two pause cycles
		SPHY Mode:
		Selects the maximum burst size on the RX path
		for port 3.
23:22	RX_BURST Port 3	0x = 64 bytes maximum burst size	R/W	0x0
		10 = 128 bytes maximum burst size
		11 = 256 bytes maximum burst size
		MPHY Mode:
		NA
		SPHY Mode:
		Selects the maximum burst size on the RX path
		for port 2.
21:20	RX_BURST Port 2	0x = 64 bytes maximum burst size	R/W	0x0
		10 = 128 bytes maximum burst size
		11 = 256 bytes maximum burst size
		MPHY Mode:
		NA
		SPHY Mode:
		Selects the maximum burst size on the RX path
		for port 1.
19:18	RX_BURST Port 1	0x = 64 bytes maximum burst size	R/W	0x0
		10 = 128 bytes maximum burst size
		11 = 256 bytes maximum burst size
		MPHY Mode:
		NA

1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write

Datasheet 215

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004