Contents |
| |
83 | Flush TX ($ Port_Index + 0x11) | 166 |
84 | FC Enable ($ Port_Index + 0x12) | 167 |
85 | FC Back Pressure Length ($ Port_Index + 0x13) | 167 |
86 | Short Runts Threshold ($ Port_Index + 0x14) | 168 |
87 | Discard Unknown Control Frame ($ Port_Index + 0x15) | 168 |
88 | RX Config Word ($ Port_Index + 0x16) | 168 |
89 | TX Config Word ($ Port_Index + 0x17) | 169 |
90 | Diverse Config Write ($ Port_Index + 0x18) | 170 |
91 | RX Packet Filter Control ($ Port_Index + 0x19) | 171 |
92 | Port Multicast Address ($ Port_Index +0x1A – +0x1B) | 172 |
93 | MAC RX Statistics ($ Port_Index + 0x20 – + 0x39) | 173 |
94 | MAC TX Statistics ($ Port_Index +0x40 – +0x58) | 177 |
95 | PHY Control ($ Port Index + 0x60) | 180 |
96 | PHY Status ($ Port Index + 0x61) | 181 |
97 | PHY Identification 1 ($ Port Index + 0x62) | 182 |
98 | PHY Identification 2 ($ Port Index + 0x63) | 182 |
99 | 183 | |
100 | 184 | |
101 | 185 | |
102 | 186 | |
103 | Port Enable ($0x500) | 187 |
104 | Interface Mode ($0x501) | 187 |
105 | Link LED Enable ($0x502) | 188 |
106 | MAC Soft Reset ($0x505) | 188 |
107 | MDIO Soft Reset ($0x506) | 189 |
108 | CPU Interface ($0x508) | 189 |
109 | LED Control ($0x509) | 189 |
110 | LED Flash Rate ($0x50A) | 190 |
111 | LED Fault Disable ($0x50B) | 190 |
112 | JTAG ID ($0x50C) | 191 |
113 | RX FIFO High Watermark Port 0 ($0x580) | 192 |
114 | RX FIFO High Watermark Port 1 ($0x581) | 192 |
115 | RX FIFO High Watermark Port 2 ($0x582) | 192 |
116 | RX FIFO High Watermark Port 3 ($0x583) | 193 |
117 | RX FIFO Low Watermark Port 0 ($0x58A) | 193 |
118 | RX FIFO Low Watermark Port 1 ($0x58B) | 193 |
119 | RX FIFO Low Watermark Port 2 ($0x58C) | 194 |
120 | RX FIFO Low Watermark Port 3 ($0x58D) | 194 |
121 | RX FIFO Overflow Frame Drop Counter Ports 0 - 3 ($0x594 – 0x597) | 194 |
122 | RX FIFO Port Reset ($0x59E) | 195 |
123 | RX FIFO Errored Frame Drop Enable ($0x59F) | 195 |
124 | RX FIFO Overflow Event ($0x5A0) | 196 |
125 | RX FIFO Errored Frame Drop Counter Ports 0 - 3 ($0x5A2 - 0x5A5) | 197 |
126 | RX FIFO SPI3 Loopback Enable for Ports 0 - 3 ($0x5B2) | 198 |
127 | RX FIFO Padding and CRC Strip Enable ($0x5B3) | 199 |
128 | RX FIFO Transfer Threshold Port 0 ($0x5B8) | 200 |
129 | RX FIFO Transfer Threshold Port 1 ($0x5B9) | 200 |
130 | RX FIFO Transfer Threshold Port 2 ($0x5BA) | 201 |
131 | RX FIFO Transfer Threshold Port 3 ($0x5BB) | 201 |
132 | TX FIFO High Watermark Ports 0 - 3 ($0x600 – 0x603) | 202 |
10 |
| Datasheet |
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004
