Intel IXF1104 manual 5.4.2Timing Specifics, 5.4.3TX_ER and RX_ER Coding, Datasheet

Models: IXF1104

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5.4.2Timing Specifics

IXF1104 Quad-Port 10/100/1000 Mbps Ethernet Media Access Controller

5.4.2Timing Specifics

The IXF1104 RGMII complies with RGMII Rev1.2a requirements. Table 27 provides the timing specifics.

5.4.3TX_ER and RX_ER Coding

To reduce interface power, the transmit error condition (TX_ER) and the receive error condition (RX_ER) are encoded on the RGMII interface to minimize transitions during normal network operation (refer to Table 28 on page 96 for the encoding method). Table 27 provides signal definitions for RGMII.

Table 27. RGMII Signal Definitions

IXF1104

RGMII

 

 

Standard

Source

Description

Signal

Signal

 

 

 

 

 

 

 

 

 

TXC_0:3

TXC

MAC

Depending on speed, the transmit reference clock is 125 MHz, 25 MHz,

or 2.5 MHz +/– 50ppm.

 

 

 

 

 

 

 

TD[3:0]_n

TD<3:0>

MAC

Contains register bits 3:0 on the rising edge of TXC and register bits 7:4

on the falling edge of TXC.

 

 

 

 

 

 

 

TX_EN

TX_CTL

MAC

TXEN is on the leading edge of TXC.

TX_EN xor TX_ER is on the falling edge of TXC.

 

 

 

 

 

 

 

RXC_0:3

RXC

PHY

Continuous reference clock is 125 MHz, 25 MHz, or 2.5 MHz +/– 50

ppm.

 

 

 

 

 

 

 

RD[3:0]_n

RD<3:0>

PHY

Contains register bits 3:0 on the leading edge of RXC and register bits

7:4 on the trailing edge of RXC.

 

 

 

 

 

 

 

RX_DV

RX_CTL

PHY

RX_DV is on the leading edge of RXC.

RX_DV or RXERR is the falling edge of RXC.

 

 

 

 

 

 

 

The value of RGMII_TX_ER and RGMII_TX_EN are valid at the rising edge of the clock while TX_ER is presented on the falling edge of the clock. RX_ER coding behaves in the same way (see Table 28, Figure 19, and Figure 20).

Table 28. TX_ER and RX_ER Coding Description

Condition

 

Description

 

 

 

 

Receiving valid frame,

RX_DV = true

 

RX_ER = false

no errors

Logic High on rising edge of RXC

 

Logic High on the falling edge of RXC

 

 

 

 

Receiving valid frame,

RX_DV = true

 

RX_ER = true

with errors

Logic High on rising edge of RXC

 

Logic Low on the falling edge of RXC

 

 

 

 

Receiving invalid frame

RX_DV = false

 

RX_ER = false

(or no frame)

Logic Low on rising edge of RXC

 

Logic Low on the falling edge of RXC

 

 

 

 

Transmitting valid frame,

TX_EN = true

 

TX_ER =false

no errors

Logic High on rising edge of TXC

 

Logic High on the falling edge of TXC

 

 

 

 

Transmitting valid frame

TX_EN = true

 

TX_ER = true

with errors

Logic High on rising edge of TXC

 

Logic Low on the falling edge of TXC

 

 

 

 

Transmitting invalid

TX_EN = false

 

TX_ER = false

frame (or no frame)

Logic Low on rising edge of TXC

 

Logic low on the falling edge of TXC

 

 

 

NOTE: Refer to Figure 19 for TX_CTL behavior, and Figure 20 for RX_CTL behavior.

 

 

 

 

96

Datasheet

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004

Page 96
Image 96
Intel IXF1104 manual 5.4.2Timing Specifics, 5.4.3TX_ER and RX_ER Coding, Datasheet