IXF1104
7.9Transmit Pause Control AC Timing Specification
Figure 49 and Table 55 show the pause control AC timing specifications. The Pause Control interface operates as an asynchronous interface relative to the main system clock (CLK125). There is, however, a relationship between the TXPAUSEADD bus and the strobe signal (TXPAUSEFR).
Figure 49. Pause Control Interface Timing
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| TxPauseAdd[1:0]TXPAUSEADD[2:0] | |
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| TxPauseFr |
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000 | Tsu(min) = 16 ns | Tpw(min) = 16 ns | Thold(min) = 16 ns |
: XON packet on all ports |
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001 | : XOFF Port0 |
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010 | : XOFF Port1 |
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011 | : XOFF Port2 |
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100 | : XOFF Port3 |
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111 | : XOFF on all ports |
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Table 55. Transmit Pause Control Interface Timing Parameters
Symbol | Parameter | Min | Max | Units |
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Tsu | TXPAUSEADD stable prior to TXPAUSEFR High | 16 | – | ns |
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Tpw | TXPAUSEFR pulse width | 16 | – | ns |
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Thold | TXPAUSEADD stable after TXPAUSEFR High | 16 | – | ns |
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150 | Datasheet |
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004