Intel IXF1104 manual Datasheet, Register Description: TX FIFO Underflow Event

Models: IXF1104

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Register Description: TX FIFO Underflow Event:

IXF1104 4-Port Gigabit Ethernet Media Access Controller

Table 135. TX FIFO Overflow/Underflow/Out of Sequence Event ($0x61E) (Sheet 1 of 2)

Bit

Name

Description

 

Type1

Default

 

 

 

 

 

 

Register Description: TX FIFO Out of Sequence Event:

 

 

These register bits provide status information, and indicate if out-of-sequence data has been

0x0

received. The bit position equals the port number + 8. These bits are cleared on Read.

 

 

 

 

 

Register Description: TX FIFO Underflow Event:

 

 

This register provides a status that a FIFO Empty situation has occurred (for example, a FIFO

0x0

under-run). The bit position equals the port number + 4. This register is cleared on Read.

 

 

 

 

Register Description: TX FIFO Overflow Event:

 

 

This register provides a status that a FIFO full situation has occurred (for example, a FIFO

0x0

overflow). The bit position equals the port number. This register is cleared on Read.

 

 

 

 

 

 

 

 

31:12

Reserved

Reserved

 

RO

0x00000

 

 

 

 

 

 

 

 

Port 3

 

 

 

11

FOSE3

0 = FIFO out of sequence event did not occur

 

R

0

 

 

1 = FIFO out of sequence event occurred

 

 

 

 

 

 

 

 

 

 

 

Port 2

 

 

 

10

FOSE2

0 = FIFO out of sequence event did not occur

 

R

0

 

 

1 = FIFO out of sequence event occurred

 

 

 

 

 

 

 

 

 

 

 

Port 1

 

 

 

9

FOSE1

0 = FIFO out of sequence event did not occur

 

R

0

 

 

1 = FIFO out of sequence event occurred

 

 

 

 

 

 

 

 

 

 

 

Port 0

 

 

 

8

FOSE0

0 = FIFO out of sequence event did not occur

 

R

0

 

 

1 = FIFO out of sequence event occurred

 

 

 

 

 

 

 

 

 

 

 

Port 3

 

 

 

7

FUE3

0 = FIFO underflow event did not occur

 

R

0

 

 

1 = FIFO underflow event occurred

 

 

 

 

 

 

 

 

 

 

 

Port 2

 

 

 

6

FUE2

0 = FIFO underflow event did not occur

 

R

0

 

 

1 = FIFO underflow event occurred

 

 

 

 

 

 

 

 

 

 

 

Port 1

 

 

 

5

FUE1

0 = FIFO underflow event did not occur

 

R

0

 

 

1 = FIFO underflow event occurred

 

 

 

 

 

 

 

 

 

 

 

Port 0

 

 

 

4

FUE0

0 = FIFO underflow event did not occur

 

R

0

 

 

1 = FIFO underflow event occurred

 

 

 

 

 

 

 

 

 

 

 

Port 3

 

 

 

3

FOE3

0 = FIFO overflow event did not occur

 

R

0

 

 

1 = FIFO overflow event occurred

 

 

 

 

 

 

 

 

 

1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write

Datasheet

205

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004

Page 205
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Intel IXF1104 manual Datasheet, Register Description: TX FIFO Underflow Event, Register Description: TX FIFO Overflow Event