Intel IXF1104 manual Datasheet, Source Synchronous Transmit Clock, Transmit Data, Transmit Control

IXF1104 4-Port Gigabit Ethernet Media Access Controller

Table 6. RGMII Interface Signal Descriptions (Sheet 1 of 2)

Signal Name	Ball	Type	Standard	Description
	Designator
TXC_0	AA1			Source Synchronous Transmit Clock.
TXC_1	AD7		2.5 V
		Output		This clock is supplied synchronous to the transmit
TXC_2	AC20		CMOS
				data bus in either RGMII or GMII mode.
TXC_3	AB14
TD3_0	AA3
TD2_0	Y3
TD1_0	Y2
TD0_0	Y1
TD3_1	AD9
TD2_1	AB9			Transmit Data.
TD1_1	AB7
				Bits [3:0] are clocked on the rising edge of TXC.
TD0_1	AC7
		Output	2.5 V	Bits [7:4] are clocked on the falling edge of TXC.
			CMOS
TD3_2	AB23
				NOTE: Shares data signals TXD[3:0]_n with the
TD2_2	AB22
				GMII interface.
TD1_2	AB21
TD0_2	AB20
TD3_3	V17
TD2_3	V16
TD1_3	V15
TD0_3	V14
				Transmit Control.
TX_CTL_0	AB2			TX_CTL is TX_EN on the rising edge of TXC and a
				logical derivative of TX_EN and TX_ER on the
TX_CTL_1	Y8		2.5 V
		Output		falling edge of TXC.
TX_CTL_2	AC22		CMOS
TX_CTL_3	V12			NOTE: TX_CTL multiplexes with TX_EN_n on the
				GMII interface.
				Receiver Reference Clock.
				Operates at:
RXC_0	V4			125 MHz for 1 Gigabit
RXC_1	AD11	Input	2.5 V	25 MHz for 100 Mbps
RXC_2	AA24		CMOS	2.5 MHz for 10 Mbps
RXC_3	V23
				NOTE: Shares the same balls as RXC on the
				GMII interface.

Datasheet 49

Document Number: 278757

Revision Number: 007

Revision Date: March 25, 2004