IXF1104
Table 107. MDIO Soft Reset ($0x506)
Bit | Name | Description | Type1 | Default | ||
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Register Description: |
| 0x00000000 | ||||
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31:1 | Reserved | Reserved | RO | 0x00000000 | ||
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0 | Software MDIO Reset | 0 = | Reset inactive | R/W | 0 | |
1 = | Reset active | |||||
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1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write
Table 108. CPU Interface ($0x508)
Bit | Name | Description | Type1 | Default | ||
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Register Description: CPU Interface Endian select. Allows the user to select the Endian of | 0x00000000 | |||||
the CPU interface to allow for various CPUs to be connected to the IXF1104. |
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31:25 | Reserved | Reserved | RO | 0x00 | ||
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| Reserved in Little Endian |
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24 | CPU Endian | Valid in Big endian | R/W | 0 | ||
0 = | Little Endian | |||||
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| 1 = | Big Endian |
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23:1 | Reserved | Reserved | RO | 0x000000 | ||
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| Reserved in Big Endian |
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0 | CPU Endian Control | Valid in Little Endian | R/W | 0 | ||
0 = | Little Endian | |||||
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| 1 = | Big Endian |
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1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write
NOTE: Since the Endianess of the bus is unknown when writing to this register, write 0x01000001 to set the bit and 0x0 to clear it.
Table 109. LED Control ($0x509)
Bit | Name | Description | Type1 | Default | |
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Register Description: Global selection of LED mode. |
| 0x00000000 | |||
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31:2 | Reserved | Reserved | RO | 0x00000000 | |
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1 | LED Enable | 0 = Disable LED Block | R/W | 0 | |
1 = Enable LED Block | |||||
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| 0 = Enable LED Mode 0 for use with SGS |
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0 | LED Control | Thomson M5450 LED driver (Default) | R/W | 0 | |
1 = LED Mode 1 for use with Standard Octal Shift | |||||
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1.RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No clear; R/W/C = Read/Write, Clear on Write
Datasheet | 189 |
Document Number: 278757
Revision Number: 007
Revision Date: March 25, 2004