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Intel 5. GD82559ER Test Port Functionality, Introduction, Asynchronous Test Mode, 5.4 85/85

Models: GD82559ER

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Networking Silicon — GD82559ER

5.GD82559ER Test Port Functionality

5.1Introduction

The 82559ER’s NAND-Tree Test Access Port (TAP) is the access point for test data to and from the device. The port provides the ability to perform basic production level testing. The port pro- vides two functions:

1)The the synchronous IC validation mode used in the production of the device. This mode gives the signals their names (i.e TCK, Testability Port Clock).

2)In addition to the synchronous test mode, the 82559ER supports asynchonous testing modes. These test modes support the validation of connections at the board level.

5.2Asynchronous Test Mode

Four asynchronous test modes are supported for system level design use. The modes are selected through the use of Test Port input pin in static combinations. The Test Port pins are: TEST, TI, TEXEC and TCK. During normal operation the Test pin must be pulled down through a resistor (pulling Test high enables the test mode). All other Port inputs may have a pull-down at the design- ers discretion.

5.3Test Function Description

The 82559 TAP mode supports several tests that can be used in board level design. These tests can help in the verification of basic functionality. As well as test the integrity of solder connection on the board. The tests are as follows:

5.485/85

The 85/85 test provides the same functionality to the board level designer as the Tristate mode. This mode is normal used during chip the chip burn-in cycling. The 82559ER is placed in this mode during the 85o/85% humidity test cycling. Test Pin Combinations: TEST = ‘1, TCK = ‘0, TEXEC = ‘1, TI = ‘1

Datasheet

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Intel 5. GD82559ER Test Port Functionality, Introduction, Asynchronous Test Mode, Test Function Description, 5.4 85/85

Contents

Networking Silicon Product FeaturesDatasheet GD82559ER Fast Ethernet PCI ControllerDate DatasheetGD82559ER - Networking Silicon Revision HistorySIGNAL DESCRIPTIONS ContentsINTRODUCTION DatasheetGD82559ER - Networking Silicon PCI CONFIGURATION REGISTERSCONTROL/STATUS REGISTERS Datasheet8.1.10 10. ELECTRICAL AND TIMING SPECIFICATIONSNetworking Silicon - GD82559ER DatasheetGD82559ER - Networking Silicon DatasheetDatasheet 1. Introduction1.1 GD82559ER Overview 1.2 Suggested ReadingDatasheet GD82559ER - Networkin g SiliconDatasheet Figure 1. 82559ER Block Diagram2. GD82559ER Architectural Overview 2.1 Parallel Subsystem Overview2.2 FIFO Subsystem Overview DatasheetGD82559ER - Networkin g Silicon Networking Silicon - GD82559ER 2.3 10/100 Mbps Serial CSMA/CD Unit Overview2.4 10/100 Mbps Physical Layer Unit DatasheetGD82559ER - Networkin g Silicon Datasheet3.2.1 Address and Data Signals 3. Signal Descriptions3.1 Signal Type Definitions 3.2 PCI Bus Interface Signals3.2.2 Interface Control Signals DatasheetGD82559ER - Networkin g Silicon Flash Address15/EEPROM Data Output. During Flash accesses 3.3 Local Memory Interface Signals3.2.3 System and Power Management Signals DatasheetGD82559ER - Networkin g Silicon 3.4 Testability Port SignalsDatasheet Flash Address13/EEPROM Data Input. During Flash accessesReference Bias Resistor 100 Mbps. This pin controls the out 3.5 PHY SignalsDatasheet Networking Silicon -GD82559ERGD82559ER - Networkin g Silicon DatasheetDatasheet 4. GD82559ER Media Access Control Functional Description4.1 82559ER Initialization 4.1.1 Initialization Effects on 82559ER Units4.2.1.1 82559ER Bus Slave Operation 4.2.1.1.1 Control/Status Register CSR Accesses4.2 PCI Interface 4.2.1 82559ER Bus OperationsFigure 3. CSR I/O Write Cycle SYSTEM82559ER Figure 2. CSR I/O Read CycleGD82559ER - Networkin g Silicon 4.2.1.1.2 Flash Buffer AccessesFigure 4. Flash Buffer Read Cycle DatasheetNetworking Silicon - GD82559ER 4.2.1.1.3 Retry Premature AccessesFigure 5. Flash Buffer Write Cycle DatasheetFigure 6. PCI Retry Cycle 4.2.1.1.4 Error Handling4.2.1.2 82559ER Bus Master Operation 82559ER SYSTEMNetworking Silicon - GD82559ER Figure 7. Memory Read Burst CycleFigure 8. Memory Write Burst Cycle Datasheet4.2.1.2.1 Memory Write and Invalidate DatasheetGD82559ER - Networkin g Silicon 4.2.1.2.2 Read Align DatasheetNetworking Silicon - GD82559ER Datasheet 4.2.2 Clockrun Signal4.2.3 Power Management Event Signal 4.2.1.2.3 Error Handling4.2.4.3 D2 Power State 4.2.4 Power States4.2.4.1 D0 Power State 4.2.4.2 D1 Power StatePower State 4.2.4.4 D3 Power State4.2.4.5 Understanding Power Requirements DatasheetDatasheet 4.2.4.6 Auxiliary Power Signal4.2.4.7 Alternate Reset Signal 4.2.4.7.1 Isolate SignalGD82559ER - Networkin g Silicon 4.2.4.7.2 PCI Reset SignalFigure 9. Isolate Signal Behavior to PCI Power Good Signal DatasheetDatasheet 4.2.5 Wake-up Events4.2.5.1 “Interestin g” Packet Events Figure 10. 82559ER Initialization upon PCI RST# and ISOLATE#Datasheet 4.3 Parallel Flash Interface4.4 Serial EEPROM Interface 4.2.5.2 Link Status Change EventNetworking Silicon - GD82559ER Figure 11. 64 Word EEPROM Read Instruction WaveformFigure 12. 82559ER EEPROM Format DatasheetWord 4.5 10/100 Mbps CSMA/CD UnitTable 1. EEPROM Words Field Descriptions Datasheet4.5.4 Long Frame Reception 4.5.1 Full Duplex4.5.2 Flow Control 4.5.3 Address Filtering Modifications4.6 Media Independent Interface MII Management Interface DatasheetGD82559ER - Networkin g Silicon 5.3 Test Function Description 5. GD82559ER Test Port Functionality5.1 Introduction 5.2 Asynchronous Test ModeDatasheet 5.5 TriState5.6 Nand - Tree Table 2. Nand - Tree ChainsFLA0 DatasheetNetworking Silicon - GD82559ER Table 2. Nand - Tree ChainsGD82559ER - Networkin g Silicon Datasheet6.1.2 100BASE-TX Transmit Blocks 6. GD82559ER Physical Layer Functional Description6.1 100BASE-TX PHY Unit 6.1.1 100BASE-TX Transmit Clock GenerationTable 3. 4B/5B Encoder 6.1.2.2 100BASE-TX Scrambler and MLT-3 EncoderDatasheet GD82559ER - Networkin g SiliconFigure 14. Conceptual Transmit Differential Waveform Figure 13. NRZ to MLT-3 Encoding Diagram6.1.2.3 100BASE-TX Transmit Framing 6.1.2.4 Transmit Driver6.1.3.1 Adaptive Equalizer 6.1.3.2 Receive Clock and Data Recovery6.1.3.5 100BASE-TX Receive Error Detection and Reporting 6.1.3 100BASE-TX Receive Blocks6.1.6 Auto 10/100 Mbps Speed Selection 6.1.5 100BASE-TX Link Integrity and Auto-Negotiation Solution6.2 10BASE-T Functionality 6.1.4 100BASE-TX Collision Detection6.2.2.2 10BASE-T Driver and Filter 6.2.2 10BASE-T Transmit Blocks6.2.3 10BASE-T Receive Blocks 6.2.2.1 10BASE-T Manchester Encoder6.2.5 10BASE-T Link Integrity 6.2.3.3 10BASE-T Error Detection and Reporting6.3 Auto-Negotiation Functionality 6.2.4 10BASE-T Collision DetectionGD82559ER - Networkin g Silicon 6.3.1 Description6.3.2 Parallel Detect and Auto-Negotiation DatasheetNetworking Silicon - GD82559ER 6.4 LED DescriptionFigure 15. Auto-Negotiation and Parallel Detect DatasheetLILED Figure 16. Two and Three LED Schematic DiagramDatasheet GD82559ER - Networkin g Silicon7.1.1 PCI Vendor ID and Device ID Registers 7. PCI Configuration Registers7.1 LAN Ethernet PCI Configuration Space Figure 17. PCI Configuration RegistersFigure 18. PCI Command Register 7.1.2 PCI Command RegisterSERR# Enable Parity Error Response Memory Write and Invalidate Enable Bus Master Enable Memory Space IO spaceTable 6. PCI Status Register Bits 7.1.3 PCI Status Register1 0 Figure 19. PCI Status RegisterFigure 20. Cache Line Size Register 7.1.4 PCI Revision ID Register7.1.5 PCI Class Code Register 7.1.6 PCI Cache Line Size RegisterFigure 21. Base Address Register for Memory Mapping 7.1.7 PCI Latency Timer7.1.8 PCI Header Type 7.1.9 PCI Base Address Registers7.1.9.4 Expansion ROM Base Address Register 7.1.9.1 CSR Memory Mapped Base Address Register7.1.9.2 CSR I/O Mapped Base Address Register 7.1.9.3 Flash Memory Mapped Base Address RegisterTable 7. 82559ER ID Fields Programming 7.1.10 PCI Subsystem Vendor ID and Subsystem ID Registers7.1.11 Capability Pointer 7.1.12 Interrupt Line Register7.1.14 Minimum Grant Register 7.1.18 Power Management Capabilities RegisterTable 8. Power Management Capability Register 7.1.13 Interrupt Pin RegisterDatasheet 7.1.19 Power Management Control/Status Register PMCSRTable 9. Power Management Control and Status Register Table 8. Power Management Capability RegisterGD82559ER - Networkin g Silicon 7.1.20 Data RegisterTable 10. Ethernet Data Register DatasheetFigure 23. 82559ER Control/Status Register SCB Status Word SCB Command Word SCB General Pointer PORT Interface8. Control/Status Registers 8.1 LAN Ethernet Control/Status RegistersGD82559ER - Networking Silicon 8.1.1 System Control Block Status WordReceive DMA Byte Count Flow Control Register PMDR Datasheet8.1.5 Flash Control Register 8.1.2 System Control Block Command Word8.1.3 System Control Block General Pointer 8.1.4 PORT8.1.9 Early Receive Interrupt 8.1.8 Receive Direct Memory Access Byte Count8.1.11 Power Management Driver Register Table 11. Power Management Driver RegisterTable 13. General Status Register 8.1.12 General Control Register8.1.13 General Status Register Table 12. General Control RegisterGD82559ER - Networking Silicon 8.2 Statistical CountersTable 14. 82559ER Statistical Counters Datasheetframes. These frames are valid MAC control frames that have DatasheetTable 14. 82559ER Statistical Counters follow the first are also lost however, because there is no lostGD82559ER - Networking Silicon DatasheetDatasheet 9. PHY Unit Registers9.1 MDI Registers 0 9.1.1 Register 0 Control Register Bit DefinitionsThis bit restarts the Auto-Negotiation process and is self 9.1.2 Register 1 Status Register Bit DefinitionsDatasheet GD82559ER - Networking SiliconNetworking Silicon - GD82559ER 9.1.3 Register 2 PHY Identifier Register Bit Definitions9.1.4 Register 3 PHY Identifier Register Bit Definitions DatasheetDatasheet 9.2 MDI Registers 89.3 MDI Register 16 9.1.7 Register 6 Auto-Negotiation Expansion Register Bit Definitions9.3.2 Register 17 PHY Unit Special Control Bit Definitions DatasheetNetworking Silicon - GD82559ER 9.3.5 Register 21 100BASE-TX Receive Error Frame Counter Bit9.3.7 Register 22 Receive Symbol Error Counter Bit Definitions 9.3.3 Register 18 PHY Address RegisterCounter Bit Definitions Register 23 100BASE-TX Receive Premature End of Frame ErrorRegister 24 10BASE-T Receive End of Frame Error Counter Bit 9.3.8GD82559ER - Networking Silicon DatasheetTable 16. PCI Interface DC Specifications 10. Electrical and Timing Specifications10.2 DC Specifications Table 15. General DC SpecificationsTable 16. PCI Interface DC Specifications Table 17. Flash/EEPROM Interface DC SpecificationsTable 18. LED Voltage/Current Characteristics Table 19. 100BASE-TX Voltage/Current CharacteristicsDatasheet Table 20. 10BASE-T Voltage/Current CharacteristicsFigure 24. RBIAS100 Resistance Versus Transmitter Current Table 19. 100BASE-TX Voltage/Current CharacteristicsDatasheet 10.3 AC SpecificationsTable 21. AC Specifications for PCI Signaling Figure 25. RBIAS10 Resistance Versus Transmitter Current10.4.1.2 X1 Specifications 10.4 Timing Specifications10.4.1 Clocks Specifications 10.4.1.1 PCI Clock SpecificationsFigure 28. Input Timing Measurement Conditions 10.4.2 Timing Parameters10.4.2.1 Measurement and Test Conditions Figure 27. Output Timing Measurement ConditionsDatasheet 10.4.2.2 PCI Timings10.4.2.3 Flash Interface Timings Table 25. PCI Timing ParametersTable 26. Flash Timing Parameters DatasheetGD82559ER - Networking Silicon Datasheet 10.4.2.4 EEPROM Interface TimingsFigure 29. Flash Timings for a Read Cycle Table 27. EEPROM Timing ParametersFigure 31. 10BASE-T NLP Timings 10.4.2.5 PHY TimingsFigure 30. EEPROM Timings Table 28. 10BASE-T NLP Timing ParametersNetworking Silicon - GD82559ER Table 30. 100Base-TX Transmitter AC SpecificationFigure 32. Auto-Negotiation FLP Timings DatasheetGD82559ER - Networking Silicon DatasheetDatasheet Figure 24. Dimension Diagram for the GD82559ER 196-Pin BGA12. Package and Pinout Information 12.1 Package InformationDatasheet 12.2 Pinout Information12.2.1 GD82559ER Pin Assignments Table 15. GD82559ER Pin AssignmentsDatasheet Networking Silicon - GD82559ERTable 15. GD82559ER Pin Assignments GD82559ER - Networking Silicon 12.2.2 GD82559ER Ball Grid Array DiagramFigure 25. GD82559ER Ball Grid Array Diagram Datasheet