Networking Silicon — GD82559ER
Commands for the 82559ER’s Command and Receive units are placed in this register by the CPU.
Bits | Name | Description | |
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31:26 | Specific | Specific Interrupt Mask. Setting this bit to 1b causes the 82559ER to stop | |
generating an interrupt (in other words, | |||
Interrupt Mask | |||
| corresponding event. | ||
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25 | SI | Software Generated Interrupt. Setting this bit to 1b causes the 82559ER | |
to generate an interrupt. Writing a 0b to this bit has no effect. | |||
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| Interrupt Mask. If the Interrupt Mask bit is set to 1b, the 82559ER will not | |
24 | M | assert its INTA# pin. The M bit has higher precedence that the Specific | |
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| Interrupt Mask bits and the SI bit. | |
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23:20 | CUC | Command Unit Command. This field contains the CU command. | |
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19 | Reserved | This bit is reserved and should be set to 0b. | |
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18:16 | RUC | Receive Unit Command. This field contains the RU command. | |
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The System Control Block (SCB) General Pointer is a
The PORT interface allows software to perform certain control functions on the 82559ER. This field is 32 bits wide:
•Address and Data (bits 32:4)
•PORT Function Selection (bits 3:0)
The 82559ER supports four PORT commands: Software Reset,
The Flash Control Register is a
The EEPROM Control Register is a
EEPROM.
The Management Data Interface (MDI) Control register is a
Bits | Description |
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31:30 | These bits are reserved and should be set to 00b. |
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Datasheet | 59 |