Networking Silicon
Symbol | Type | Name and Function | |
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| Clock. The Clock signal provides the timing for all PCI transactions | |
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| and is an input signal to every PCI device. The 82559ER requires a | |
CLK | IN | PCI Clock signal (frequency greater than or equal to 16 MHz) for | |
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| nominal operation. The 82559ER supports Clock signal suspension | |
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| using the Clockrun protocol. | |
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| Clockrun. The Clockrun signal is used by the system to pause or slow | |
| IN/OUT | down the PCI Clock signal. It is used by the 82559ER to enable or | |
CLKRUN# | disable suspension of the PCI Clock signal or restart of the PCI clock. | ||
O/D | |||
| When the Clockrun signal is not used, this pin should be connected to | ||
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| an external | |
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| Reset. The PCI Reset signal is used to place PCI registers, | |
RST# | IN | sequencers, and signals into a consistent state. When RST# is | |
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| asserted, all PCI output signals will be | |
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| Power Management Event. The Power Management Event signal | |
PME# | O/D | indicates that a power management event has occurred in a PCI bus | |
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| system. | |
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| Isolate. The Isolate signal is used to isolate the 82559ER from the | |
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| PCI bus. When Isolate is active (low), the 82559ER does not drive its | |
ISOLATE# | IN | PCI outputs (except PME#) or sample its PCI inputs (including CLK | |
and RST#). If the 82559ER is not powered by an auxiliary power | |||
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| source, the ISOLATE# pin should be pulled high to the bus Vcc | |
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| through a | |
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| Alternate Reset. The Alternate Reset signal is used to reset the | |
ALTRST# | IN | 82559ER on | |
supply, ALTRST# should be connected to a | |||
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| Otherwise, ALTRST# should be tied to Vcc. | |
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| Voltage Input/Output. The VIO pin is the a voltage bias pin for the | |
| B | PCI interface. This pin should be connected to 5V ± 5% in a 5 volt PCI | |
VIO | system and 3.3 volts in a 3.3 volt PCI system. Be sure to install a 10K | ||
IN | |||
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| where the VIO bias voltage maybe shutdown. In this cases the | |
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| 82559ER may consume additional current without a resistor. | |
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Symbol | Type | Name and Function | |
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FLD[7:0] | T/S | Flash Data Input/Output. These pins are used for Flash data | |
interface. | |||
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| Flash Address[16]/25 MHz Clock. This multiplexed pin is controlled | |
FLA[16]/ | OUT | by the status of the Flash Address[7] (FLA[7]) pin. If FLA[7] is left | |
CLK25 | floating, this pin is used as FLA[16]; otherwise, if FLA[7] is connected | ||
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| to a | |
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| Flash Address[15]/EEPROM Data Output. During Flash accesses, | |
FLA[15]/ | OUT | this multiplexed pin acts as the Flash Address [15] output signal. | |
EESK | During EEPROM accesses, it acts as the serial shift clock output to | ||
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| the EEPROM. | |
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| Flash Address[14]/EEPROM Data Output. During Flash accesses, | |
FLA[14]/ | IN/OUT | this multiplexed pin acts as the Flash Address [14] output signal. | |
EEDO | During EEPROM accesses, it acts as serial input data to the EEPROM | ||
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| Data Output signal. | |
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Datasheet | 9 |