Intel GD82559ER manual Local Memory Interface Signals, System and Power Management Signals

Networking Silicon —GD82559ER

3.2.3System and Power Management Signals

Symbol	Type	Name and Function
		Clock. The Clock signal provides the timing for all PCI transactions
		and is an input signal to every PCI device. The 82559ER requires a
CLK	IN	PCI Clock signal (frequency greater than or equal to 16 MHz) for
		nominal operation. The 82559ER supports Clock signal suspension
		using the Clockrun protocol.
		Clockrun. The Clockrun signal is used by the system to pause or slow
	IN/OUT	down the PCI Clock signal. It is used by the 82559ER to enable or
CLKRUN#		disable suspension of the PCI Clock signal or restart of the PCI clock.
	O/D
		When the Clockrun signal is not used, this pin should be connected to
		an external pull-down resistor.
		Reset. The PCI Reset signal is used to place PCI registers,
RST#	IN	sequencers, and signals into a consistent state. When RST# is
		asserted, all PCI output signals will be tri-stated.
		Power Management Event. The Power Management Event signal
PME#	O/D	indicates that a power management event has occurred in a PCI bus
		system.
		Isolate. The Isolate signal is used to isolate the 82559ER from the
		PCI bus. When Isolate is active (low), the 82559ER does not drive its
ISOLATE#	IN	PCI outputs (except PME#) or sample its PCI inputs (including CLK
		and RST#). If the 82559ER is not powered by an auxiliary power
		source, the ISOLATE# pin should be pulled high to the bus Vcc
		through a 4.7K-62K resistor.
		Alternate Reset. The Alternate Reset signal is used to reset the
ALTRST#	IN	82559ER on power-up. In systems that support an auxiliary power
		supply, ALTRST# should be connected to a power-up detection circuit.
		Otherwise, ALTRST# should be tied to Vcc.
		Voltage Input/Output. The VIO pin is the a voltage bias pin for the
	B	PCI interface. This pin should be connected to 5V ± 5% in a 5 volt PCI
VIO		system and 3.3 volts in a 3.3 volt PCI system. Be sure to install a 10K
	IN	pull-up resistor. This resistor acts as a current limit resistor in system
		where the VIO bias voltage maybe shutdown. In this cases the
		82559ER may consume additional current without a resistor.

3.3Local Memory Interface Signals

Symbol	Type	Name and Function
FLD[7:0]	T/S	Flash Data Input/Output. These pins are used for Flash data
		interface.
		Flash Address[16]/25 MHz Clock. This multiplexed pin is controlled
FLA[16]/	OUT	by the status of the Flash Address[7] (FLA[7]) pin. If FLA[7] is left
CLK25		floating, this pin is used as FLA[16]; otherwise, if FLA[7] is connected
		to a pull-up resistor, this pin is used as a 25 MHz clock.
		Flash Address[15]/EEPROM Data Output. During Flash accesses,
FLA[15]/	OUT	this multiplexed pin acts as the Flash Address [15] output signal.
EESK		During EEPROM accesses, it acts as the serial shift clock output to
		the EEPROM.
		Flash Address[14]/EEPROM Data Output. During Flash accesses,
FLA[14]/	IN/OUT	this multiplexed pin acts as the Flash Address [14] output signal.
EEDO		During EEPROM accesses, it acts as serial input data to the EEPROM
		Data Output signal.

Datasheet 9