Intel GD82559ER manual Eeprom Interface Timings, Eeprom Timing Parameters

Networking Silicon — GD82559ER

10.4.2.4EEPROM Interface Timings

F L A D D R

F L C S #

F L O E #

F L D A T A - R

Address Stable

T 3 5

T 3 7

T 3 8

T 3 6

Data In

T 3 9

Figure 29. Flash Timings for a Read Cycle

The 82559ER is designed to support a standard 64x16, or 256x16 serial EEPROM. Table 27 provides the timing parameters for the EEPROM interface signals. The timing parameters are illustrated in Figure 30.

Table 27. EEPROM Timing Parameters

	Symbol	Parameter	Min	Max	Units	Notes
T50	tEFSK	Serial Clock Frequency		1	Mhz	EEPROM fsk =
						1 MHz
T51	tECSS	Delay from EECS High to EESK High	300		ns	EEPROM tcss
						= 50 ns
T52	tECSH	Delay from EESK Low to EECS Low	30		ns	EEPROM tcsh
						= 0 ns
T53	tEDIS	Setup Time of EEDI to EESK	300		ns	EEPROM tdis
						= 150 ns
T54	tEDIH	Hold Time of EEDI after EESK	300		ns	EEPROM tdih
						= 150 ms
T55	tECS	EECS Low Time	750		ns	EEPROM tcs =
						250 ns

Datasheet 81