Networking Silicon — GD82559ER
F L A D D R
F L C S #
F L O E #
F L D A T A - R
Address Stable
T 3 5
T 3 7
T 3 8
T 3 6
Data In
T 3 9
The 82559ER is designed to support a standard 64x16, or 256x16 serial EEPROM. Table 27 provides the timing parameters for the EEPROM interface signals. The timing parameters are illustrated in Figure 30.
| Symbol | Parameter | Min | Max | Units | Notes |
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T50 | tEFSK | Serial Clock Frequency |
| 1 | Mhz | EEPROM fsk = |
| 1 MHz | |||||
T51 | tECSS | Delay from EECS High to EESK High | 300 |
| ns | EEPROM tcss |
| = 50 ns | |||||
T52 | tECSH | Delay from EESK Low to EECS Low | 30 |
| ns | EEPROM tcsh |
| = 0 ns | |||||
T53 | tEDIS | Setup Time of EEDI to EESK | 300 |
| ns | EEPROM tdis |
| = 150 ns | |||||
T54 | tEDIH | Hold Time of EEDI after EESK | 300 |
| ns | EEPROM tdih |
| = 150 ms | |||||
T55 | tECS | EECS Low Time | 750 |
| ns | EEPROM tcs = |
| 250 ns |
Datasheet | 81 |