Intel GD82559ER manual Register 18 PHY Address Register, Bits

GD82559ER — Networking Silicon

Bit(s)	Name		Description	Default	R/W
0	Jabber Function	1	= Jabber disabled	0	RW
	Disable	0	= Normal Jabber operation

9.3.3Register 18: PHY Address Register

Bit(s)	Name	Description	Default	R/W
15:5	Reserved	These bits are reserved and should be set to a	0	RO
		constant ‘0’
4:0	PHY Address	These bits are set to the PHY’s address, 00001b.	1	RO

9.3.4Register 19: 100BASE-TX Receive False Carrier Counter Bit Definitions

Bit(s)	Name	Description	Default	R/W
15:0	Receive False	These bits are used for the false carrier counter.	--	RO
	Carrier			SC

9.3.5	Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions
		Bit(s)	Name	Description	Default	R/W
		15:0	Disconnect Event	This field contains a 16-bit counter that increments for	--	RO
				each disconnect event. The counter freezes when full		SC
				and self-clears on read

9.3.6	Register 21: 100BASE-TX Receive Error Frame Counter Bit
	Definitions
		Bit(s)	Name	Description	Default	R/W
		15:0	Receive Error	This field contains a 16-bit counter that increments	--	RO
			Frame	once per frame for any receive error condition (such		SC
				as a symbol error or premature end of frame) in that
				frame. The counter freezes when full and self-clears
				on read.

9.3.7Register 22: Receive Symbol Error Counter Bit Definitions

Bit(s)	Name	Description	Default	R/W
15:0	Symbol Error	This field contains a 16-bit counter that increments for	--	RO
	Counter	each symbol error. The counter freezes when full and		SC
		self-clears on read.
		In a frame with a bad symbol, each sequential six bad
		symbols count as one.

70 Datasheet