Intel 1 0, PCI Status Register Bits, Reserved, Networking Silicon - GD82559ER, Datasheet

Networking Silicon — GD82559ER

7.1.3PCI Status Register

The 82559ER Status register is used to record status information for PCI bus related events. The format of this register is shown in the figure below.

31 30 29 28 27 26 25 24 23 22 21 20 19 16

0

0 1

1 0 0 1

Reserved

Detected Parity Error

Signaled System Error

Received Master Abort

Received Target Abort

Signaled Target Abort

Devsel Timing

Parity Error Detected

Fast Back To Back (target)

Capabilities List

Figure 19. PCI Status Register

Note that bits 21, 22, 26, and 27 are set to 0b and bits 20, 23, and 25 are set to 1b. The PCI Status register bits are described in the table below.

		Table 6. PCI Status Register Bits
Bits	Name	Description
		This bit indicates whether a parity error is detected. This bit must be
		asserted by the device when it detects a parity error, even if parity error
31	Detected Parity Error	handling is disabled (as controlled by the Parity Error Response bit in the
		PCI Command register, bit 6). In the 82559ER, the initial value of the
		Detected Parity Error bit is 0b. This bit is set until cleared by writing a 1b.
		This bit indicates when the device has asserted SERR#. In the 82559ER,
30	Signaled System Error	the initial value of the Signaled System Error bit is 0b. This bit is set until
		cleared by writing a 1b.
		This bit indicates whether or not a master abort has occurred. This bit must
29	Received Master	be set by the master device when its transaction is terminated with a
	Abort	master abort. In the 82559ER, the initial value of the Received Master
		Abort bit is 0b. This bit is set until cleared by writing a 1b.
		This bit indicates that the master has received the target abort. This bit
28	Received Target Abort	must be set by the master device when its transaction is terminated by a
		target abort. In the 82559ER, the initial value of the Received Target Abort
		bit is 0b. This bit is set until cleared by writing a 1b.
		This bit indicates whether a transaction was terminated by a target abort.
27	Signaled Target Abort	This bit must be set by the target device when it terminates a transaction
		with target abort. In the 82559ER, this bit is always set to 0b.
		These two bits indicate the timing of DEVSEL#:
		00b - Fast
26:25	DEVSEL# Timing	01b - Medium
		10b - Slow
		11b - Reserved
		In the 82559ER, these bits are always set to 01b, medium.

Datasheet 49