Intel GD82559ER PHY Unit Registers, MDI Registers 0, Register 0 Control Register Bit Definitions

Networking Silicon — GD82559ER

9.PHY Unit Registers

The 82559ER provides status and accepts management information via the Management Data Interface (MDI) within the CSR space.

Acronyms mentioned in the registers are defined as follows:

SC -	self cleared
RO -	read only
E -	EEPROM setting affects content
LL -	latch low
LH -	latch high

9.1MDI Registers 0 - 7

9.1.1Register 0: Control Register Bit Definitions

Bit(s)	Name		Description	Default	R/W
15	Reset	This bit sets the status and control register of the PHY to		0	RW
		their default states and is self-clearing. The PHY returns			SC
		a value of one until the reset process has completed and
		accepts a read or write transaction.
		1	= PHY Reset
14	Loopback	This bit enables loopback of transmit data nibbles from		0	RW
		the TXD[3:0] signals to the receive data path. The PHY
		unit’s receive circuitry is isolated from the network.
		Note that this may cause the descrambler to lose
		synchronization and produce 560 nanoseconds of “dead
		time.”
		Note also that the loopback configuration bit takes priority
		over the Loopback MDI bit.
		1	= Loopback enabled
		0	= Loopback disabled (Normal operation)
13	Speed Selection	This bit controls speed when Auto-Negotiation is disabled		1	RW
		and is valid on read when Auto-Negotiation is disabled.
		1	= 100 Mbps
		0	= 10 Mbps
12	Auto-Negotiation	This bit enables Auto-Negotiation. Bits 13 and 8, Speed		1	RW
	Enable	Selection and Duplex Mode, respectively, are ignored
		when Auto-Negotiation is enabled.
		1	= Auto-Negotiation enabled
		0	= Auto-Negotiation disabled
11	Power-Down	This bit sets the PHY unit into a low power mode. In low		0	RW
		power mode, the PHY unit consumes no more than 30
		mA.
		1	= Power-Down enabled
		0	= Power-Down disabled (Normal operation)
10	Reserved	This bit is reserved and should be set to 0b.		0	RW

Datasheet 65