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manual GD82559ER - Networkin g Silicon, Datasheet
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GD82559ER
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Specifications
LED Voltage/Current Characteristics
82559ER Block Diagram
Datasheet
Pci Configuration Registers
Alternate Reset Signal
PCI Command Register
Error Handling
PCI Latency Timer
Signal Descriptions
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GD82559ER — Networkin g Silicon
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Datasheet
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Contents
Product Features
Datasheet
GD82559ER Fast Ethernet PCI Controller
Networking Silicon
Datasheet
GD82559ER - Networking Silicon
Revision History
Date
Contents
INTRODUCTION
Datasheet
SIGNAL DESCRIPTIONS
PCI CONFIGURATION REGISTERS
CONTROL/STATUS REGISTERS
Datasheet
GD82559ER - Networking Silicon
10. ELECTRICAL AND TIMING SPECIFICATIONS
Networking Silicon - GD82559ER
Datasheet
8.1.10
Datasheet
GD82559ER - Networking Silicon
1. Introduction
1.1 GD82559ER Overview
1.2 Suggested Reading
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GD82559ER - Networkin g Silicon
Datasheet
Figure 1. 82559ER Block Diagram
2. GD82559ER Architectural Overview
2.1 Parallel Subsystem Overview
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GD82559ER - Networkin g Silicon
2.2 FIFO Subsystem Overview
Datasheet
2.3 10/100 Mbps Serial CSMA/CD Unit Overview
2.4 10/100 Mbps Physical Layer Unit
Datasheet
Networking Silicon - GD82559ER
Datasheet
GD82559ER - Networkin g Silicon
3. Signal Descriptions
3.1 Signal Type Definitions
3.2 PCI Bus Interface Signals
3.2.1 Address and Data Signals
GD82559ER - Networkin g Silicon
3.2.2 Interface Control Signals
Datasheet
3.3 Local Memory Interface Signals
3.2.3 System and Power Management Signals
Datasheet
Flash Address15/EEPROM Data Output. During Flash accesses
3.4 Testability Port Signals
Datasheet
Flash Address13/EEPROM Data Input. During Flash accesses
GD82559ER - Networkin g Silicon
3.5 PHY Signals
Datasheet
Networking Silicon -GD82559ER
Reference Bias Resistor 100 Mbps. This pin controls the out
Datasheet
GD82559ER - Networkin g Silicon
4. GD82559ER Media Access Control Functional Description
4.1 82559ER Initialization
4.1.1 Initialization Effects on 82559ER Units
Datasheet
4.2.1.1.1 Control/Status Register CSR Accesses
4.2 PCI Interface
4.2.1 82559ER Bus Operations
4.2.1.1 82559ER Bus Slave Operation
SYSTEM
82559ER
Figure 2. CSR I/O Read Cycle
Figure 3. CSR I/O Write Cycle
4.2.1.1.2 Flash Buffer Accesses
Figure 4. Flash Buffer Read Cycle
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GD82559ER - Networkin g Silicon
4.2.1.1.3 Retry Premature Accesses
Figure 5. Flash Buffer Write Cycle
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Networking Silicon - GD82559ER
4.2.1.1.4 Error Handling
4.2.1.2 82559ER Bus Master Operation
82559ER SYSTEM
Figure 6. PCI Retry Cycle
Figure 7. Memory Read Burst Cycle
Figure 8. Memory Write Burst Cycle
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Networking Silicon - GD82559ER
GD82559ER - Networkin g Silicon
4.2.1.2.1 Memory Write and Invalidate
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Networking Silicon - GD82559ER
4.2.1.2.2 Read Align
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4.2.2 Clockrun Signal
4.2.3 Power Management Event Signal
4.2.1.2.3 Error Handling
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4.2.4 Power States
4.2.4.1 D0 Power State
4.2.4.2 D1 Power State
4.2.4.3 D2 Power State
4.2.4.4 D3 Power State
4.2.4.5 Understanding Power Requirements
Datasheet
Power State
4.2.4.6 Auxiliary Power Signal
4.2.4.7 Alternate Reset Signal
4.2.4.7.1 Isolate Signal
Datasheet
4.2.4.7.2 PCI Reset Signal
Figure 9. Isolate Signal Behavior to PCI Power Good Signal
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GD82559ER - Networkin g Silicon
4.2.5 Wake-up Events
4.2.5.1 “Interestin g” Packet Events
Figure 10. 82559ER Initialization upon PCI RST# and ISOLATE#
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4.3 Parallel Flash Interface
4.4 Serial EEPROM Interface
4.2.5.2 Link Status Change Event
Datasheet
Figure 11. 64 Word EEPROM Read Instruction Waveform
Figure 12. 82559ER EEPROM Format
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Networking Silicon - GD82559ER
4.5 10/100 Mbps CSMA/CD Unit
Table 1. EEPROM Words Field Descriptions
Datasheet
Word
4.5.1 Full Duplex
4.5.2 Flow Control
4.5.3 Address Filtering Modifications
4.5.4 Long Frame Reception
GD82559ER - Networkin g Silicon
4.6 Media Independent Interface MII Management Interface
Datasheet
5. GD82559ER Test Port Functionality
5.1 Introduction
5.2 Asynchronous Test Mode
5.3 Test Function Description
5.5 TriState
5.6 Nand - Tree
Table 2. Nand - Tree Chains
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Datasheet
Networking Silicon - GD82559ER
Table 2. Nand - Tree Chains
FLA0
Datasheet
GD82559ER - Networkin g Silicon
6. GD82559ER Physical Layer Functional Description
6.1 100BASE-TX PHY Unit
6.1.1 100BASE-TX Transmit Clock Generation
6.1.2 100BASE-TX Transmit Blocks
6.1.2.2 100BASE-TX Scrambler and MLT-3 Encoder
Datasheet
GD82559ER - Networkin g Silicon
Table 3. 4B/5B Encoder
Figure 13. NRZ to MLT-3 Encoding Diagram
6.1.2.3 100BASE-TX Transmit Framing
6.1.2.4 Transmit Driver
Figure 14. Conceptual Transmit Differential Waveform
6.1.3.2 Receive Clock and Data Recovery
6.1.3.5 100BASE-TX Receive Error Detection and Reporting
6.1.3 100BASE-TX Receive Blocks
6.1.3.1 Adaptive Equalizer
6.1.5 100BASE-TX Link Integrity and Auto-Negotiation Solution
6.2 10BASE-T Functionality
6.1.4 100BASE-TX Collision Detection
6.1.6 Auto 10/100 Mbps Speed Selection
6.2.2 10BASE-T Transmit Blocks
6.2.3 10BASE-T Receive Blocks
6.2.2.1 10BASE-T Manchester Encoder
6.2.2.2 10BASE-T Driver and Filter
6.2.3.3 10BASE-T Error Detection and Reporting
6.3 Auto-Negotiation Functionality
6.2.4 10BASE-T Collision Detection
6.2.5 10BASE-T Link Integrity
6.3.1 Description
6.3.2 Parallel Detect and Auto-Negotiation
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GD82559ER - Networkin g Silicon
6.4 LED Description
Figure 15. Auto-Negotiation and Parallel Detect
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Networking Silicon - GD82559ER
Figure 16. Two and Three LED Schematic Diagram
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GD82559ER - Networkin g Silicon
LILED
7. PCI Configuration Registers
7.1 LAN Ethernet PCI Configuration Space
Figure 17. PCI Configuration Registers
7.1.1 PCI Vendor ID and Device ID Registers
7.1.2 PCI Command Register
SERR# Enable Parity Error Response Memory Write and Invalidate Enable
Bus Master Enable Memory Space IO space
Figure 18. PCI Command Register
7.1.3 PCI Status Register
1 0
Figure 19. PCI Status Register
Table 6. PCI Status Register Bits
7.1.4 PCI Revision ID Register
7.1.5 PCI Class Code Register
7.1.6 PCI Cache Line Size Register
Figure 20. Cache Line Size Register
7.1.7 PCI Latency Timer
7.1.8 PCI Header Type
7.1.9 PCI Base Address Registers
Figure 21. Base Address Register for Memory Mapping
7.1.9.1 CSR Memory Mapped Base Address Register
7.1.9.2 CSR I/O Mapped Base Address Register
7.1.9.3 Flash Memory Mapped Base Address Register
7.1.9.4 Expansion ROM Base Address Register
7.1.10 PCI Subsystem Vendor ID and Subsystem ID Registers
7.1.11 Capability Pointer
7.1.12 Interrupt Line Register
Table 7. 82559ER ID Fields Programming
7.1.18 Power Management Capabilities Register
Table 8. Power Management Capability Register
7.1.13 Interrupt Pin Register
7.1.14 Minimum Grant Register
7.1.19 Power Management Control/Status Register PMCSR
Table 9. Power Management Control and Status Register
Table 8. Power Management Capability Register
Datasheet
7.1.20 Data Register
Table 10. Ethernet Data Register
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GD82559ER - Networkin g Silicon
SCB Status Word SCB Command Word SCB General Pointer PORT Interface
8. Control/Status Registers
8.1 LAN Ethernet Control/Status Registers
Figure 23. 82559ER Control/Status Register
8.1.1 System Control Block Status Word
Receive DMA Byte Count Flow Control Register PMDR
Datasheet
GD82559ER - Networking Silicon
8.1.2 System Control Block Command Word
8.1.3 System Control Block General Pointer
8.1.4 PORT
8.1.5 Flash Control Register
8.1.8 Receive Direct Memory Access Byte Count
8.1.11 Power Management Driver Register
Table 11. Power Management Driver Register
8.1.9 Early Receive Interrupt
8.1.12 General Control Register
8.1.13 General Status Register
Table 12. General Control Register
Table 13. General Status Register
8.2 Statistical Counters
Table 14. 82559ER Statistical Counters
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GD82559ER - Networking Silicon
Datasheet
Table 14. 82559ER Statistical Counters
follow the first are also lost however, because there is no lost
frames. These frames are valid MAC control frames that have
Datasheet
GD82559ER - Networking Silicon
9. PHY Unit Registers
9.1 MDI Registers 0
9.1.1 Register 0 Control Register Bit Definitions
Datasheet
9.1.2 Register 1 Status Register Bit Definitions
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GD82559ER - Networking Silicon
This bit restarts the Auto-Negotiation process and is self
9.1.3 Register 2 PHY Identifier Register Bit Definitions
9.1.4 Register 3 PHY Identifier Register Bit Definitions
Datasheet
Networking Silicon - GD82559ER
9.2 MDI Registers 8
9.3 MDI Register 16
9.1.7 Register 6 Auto-Negotiation Expansion Register Bit Definitions
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Networking Silicon - GD82559ER
9.3.2 Register 17 PHY Unit Special Control Bit Definitions
Datasheet
Register 21 100BASE-TX Receive Error Frame Counter Bit
9.3.7 Register 22 Receive Symbol Error Counter Bit Definitions
9.3.3 Register 18 PHY Address Register
9.3.5
Register 23 100BASE-TX Receive Premature End of Frame Error
Register 24 10BASE-T Receive End of Frame Error Counter Bit
9.3.8
Counter Bit Definitions
Datasheet
GD82559ER - Networking Silicon
10. Electrical and Timing Specifications
10.2 DC Specifications
Table 15. General DC Specifications
Table 16. PCI Interface DC Specifications
Table 17. Flash/EEPROM Interface DC Specifications
Table 18. LED Voltage/Current Characteristics
Table 19. 100BASE-TX Voltage/Current Characteristics
Table 16. PCI Interface DC Specifications
Table 20. 10BASE-T Voltage/Current Characteristics
Figure 24. RBIAS100 Resistance Versus Transmitter Current
Table 19. 100BASE-TX Voltage/Current Characteristics
Datasheet
10.3 AC Specifications
Table 21. AC Specifications for PCI Signaling
Figure 25. RBIAS10 Resistance Versus Transmitter Current
Datasheet
10.4 Timing Specifications
10.4.1 Clocks Specifications
10.4.1.1 PCI Clock Specifications
10.4.1.2 X1 Specifications
10.4.2 Timing Parameters
10.4.2.1 Measurement and Test Conditions
Figure 27. Output Timing Measurement Conditions
Figure 28. Input Timing Measurement Conditions
10.4.2.2 PCI Timings
10.4.2.3 Flash Interface Timings
Table 25. PCI Timing Parameters
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GD82559ER - Networking Silicon
Table 26. Flash Timing Parameters
Datasheet
10.4.2.4 EEPROM Interface Timings
Figure 29. Flash Timings for a Read Cycle
Table 27. EEPROM Timing Parameters
Datasheet
10.4.2.5 PHY Timings
Figure 30. EEPROM Timings
Table 28. 10BASE-T NLP Timing Parameters
Figure 31. 10BASE-T NLP Timings
Table 30. 100Base-TX Transmitter AC Specification
Figure 32. Auto-Negotiation FLP Timings
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Networking Silicon - GD82559ER
Datasheet
GD82559ER - Networking Silicon
Figure 24. Dimension Diagram for the GD82559ER 196-Pin BGA
12. Package and Pinout Information
12.1 Package Information
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12.2 Pinout Information
12.2.1 GD82559ER Pin Assignments
Table 15. GD82559ER Pin Assignments
Datasheet
Table 15. GD82559ER Pin Assignments
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Networking Silicon - GD82559ER
12.2.2 GD82559ER Ball Grid Array Diagram
Figure 25. GD82559ER Ball Grid Array Diagram
Datasheet
GD82559ER - Networking Silicon