Intel GD82559ER PCI Interface, 4.2.1 82559ER Bus Operations, 4.2.1.1 82559ER Bus Slave Operation

GD82559ER — Networkin g Silicon

4.2PCI Interface

4.2.182559ER Bus Operations

After configuration, the 82559ER is ready for normal operation. As a Fast Ethernet controller, the role of the 82559ER is to access transmitted data or deposit received data. In both cases the 82559ER, as a bus master device, will initiate memory cycles via the PCI bus to fetch or deposit the required data.

To perform these actions, the 82559ER is controlled and examined by the CPU via its control and status structures and registers. Some of these control and status structures reside in the 82559ER and some reside in system memory. For access to the 82559ER’s Control/Status Registers (CSR), the 82559ER acts as a slave (in other words, a target device). The 82559ER serves as a slave also while the CPU accesses its 128 Kbyte Flash buffer or its EEPROM. Section 4.2.1.1 describes the 82559ER slave operation. It is followed by a description of the 82559ER operation as a bus master (initiator) in Section 4.2.1.2, “82559ER Bus Master Operation” on page 18 .

4.2.1.182559ER Bus Slave Operation

The 82559ER serves as a target device in one of the following cases:

•CPU accesses to the 82559ER System Control Block (SCB) Control/Status Registers (CSR)

•CPU accesses to the EEPROM through its CSR

•CPU accesses to the 82559ER PORT address via the CSR

•CPU accesses to the MDI control register in the CSR

•CPU accesses to the Flash control register in the CSR

•CPU accesses to the 128 Kbyte Flash

The CSR and the Flash buffer are considered by the 82559ER as two totally separated memory spaces. The 82559ER provides separate Base Address Registers (BARs) in the configuration space to distinguish between them. The size of the CSR memory space is 4 Kbyte in the memory space and 64 bytes in the I/O space. The 82559ER treats accesses to these memory spaces differently.

4.2.1.1.1Control/Status Register (CSR) Accesses

The 82559ER supports zero wait-state single-cycle memory or I/O-mapped accesses to its CSR space. Separate BARs request 4 Kbytes of memory space and 64 bytes of I/O space to accomplish this. Based on its needs, the software driver will use either memory or I/O mapping to access these registers. The 4 Kbytes of CSR space the 82559ER requests include the following elements:

•System Control Block (SCB) registers

•PORT register

•Flash control register

•EEPROM control register

•MDI control register

•Flow control registers

14 Datasheet