Intel GD82559ER manual Memory Read Burst Cycle

Networking Silicon — GD82559ER

8 depict memory read and write burst cycles. For bus master cycles, the 82559ER is the initiator and the host main memory (or the PCI host bridge, depending on the configuration of the system) is the target.

82559ER

CLK

1 2 3 4 5 6 7 8 9 10

FRAME#

SYSTEM

AD

C/BE#

IRDY#

TRDY#

DEVSEL#

ADDR

MR

DATA DATA DATA DATA DATA

BE# BE#

Figure 7. Memory Read Burst Cycle

82559ER

CLK

1 2 3 4 5 6 7 8 9 10

FRAME#

SYSTEM

AD

C/BE#

IRDY#

TRDY#

DEVSEL#

ADDR

MW

DATA DATA DATA DATA DATA

BE# BE#

Figure 8. Memory Write Burst Cycle

The CPU provides the 82559ER with action commands and pointers to the data buffers that reside in host main memory. The 82559ER independently manages these structures and initiates burst memory cycles to transfer data to and from them. The 82559ER uses the Memory Read Multiple (MR Multiple) command for burst accesses to data buffers and the Memory Read Line (MR Line) command for burst accesses to control structures. For all write accesses to the control structure, the 82559ER uses the Memory Write (MW) command. For write accesses to data structure, the 82559ER may use either the Memory Write or Memory Write and Invalidate (MWI) commands.

Read Accesses: The 82559ER performs block transfers from host system memory to perform frame transmission on the serial link. In this case, the 82559ER initiates zero wait state memory read burst cycles for these accesses. The length of a burst is bounded by the system and the 82559ER’s internal FIFO. The length of a read burst may also be bounded by the value of the Transmit DMA Maximum Byte Count in the Configure command. The Transmit DMA Maximum

Datasheet 19