Intel GD82559ER PCI Reset Signal, Isolate Signal Behavior to PCI Power Good Signal, Datasheet

GD82559ER — Networkin g Silicon

In a LAN on Motherboard solution, the PCI power good signal is supplied by the system. In network adapter implementations, the PCI power good signal can be either generated locally using an external analog device, or connected directly to the PCI reset signal. In designs, that use both the ISOLATE# and RST# pins of the 82559ER, the PCI power good signal should envelope ISOLATE#, as shown below. For designs that use the PCI reset signal, the RST# pin on the 82559ER should be tied to the PCI power rail (through a 4.7ΚΩ), and the PCI reset signal should be connected to the 82559ER’s ISOLATE# pin.

PCI power good signal

Required ISOLATE# signal behavior

Figure 9. Isolate Signal Behavior to PCI Power Good Signal

In many systems, the PCI RST# signal is asserted low whenever the PCI bus is inactive. In these systems, the 82559ER B-step device and later devices allow the ISOLATE# pin to be driven from the PCI RST# signal. In this case, the ALTRST# pin on the 82559ER should be pulled high to the PCI bus high voltage level.

4.2.4.7.2PCI Reset Signal

The PCI RST# signal may be activated in one of the following cases:

•Power-up

•Warm boot

•Wake-up (B3 to B0 transition)

•Set to power-down (B0 to B3 transition)

If PME is enabled (in the PCI power management registers), the RST# signal does not affect any PME related circuits (in other words, PCI power management registers, and the wake-up packet would not be affected). While the RST# signal is active, the 82559ER ignores other PCI signals and floats its outputs. However, if AUXPWR is asserted, the RST# signal has no affect on any circuitry.

While the 82559ER is in the D0, D1, or D2 power state, it is initialized by the RST# level. When the 82559ER is in the D3 power state, the system bus may be in the B3 bus power state. In the B3 power state, the PCI RST# signal is undefined; however, the auxiliary power source proposal for the PCI Specification, Revision 2.2 is for the PCI RST# signal to be an active low. Therefore, the 82559ER uses the PCI RST# similarly to the ISOLATE# signal in D3 power state. Following the trailing edge of the PCI RST#, the 82559ER is initialized while preserving the PME# signal and its context.

Note: According to the PCI specification, during the B3 state, the RST# signal is undefined.

The transition from the B3 power state to the B0 power state occurs on the trailing edge of the RST# signal.

The initialization signal is generated internally in the following cases:

•Active RST# signal while the 82559ER is the D0, D1, or D2 power state

•RST# trailing edge while the 82559ER is in the D3 power state

26 Datasheet