GD82559ER — Networkin g Silicon
The 82559ER link status indication circuit is capable of issuing a PME on a link status change from a valid link to an invalid link condition or vice versa. The 82559ER reports a PME link status event in all power states. The PME# signal is gated by the PME Enable bit in the PMCSR and the CSMA Configure command, which is described in the Software Developer’s Manual.
The 82559ER’s parallel interface is used primarily as a Flash interface. The 82559ER supports a glueless interface to an
The Flash (or boot PROM) is read from or written to whenever the host CPU performs a read or a write operation to a memory location that is within the Flash mapping window. All accesses to the Flash, except read accesses, require the appropriate command sequence for the device used. (Refer to the specific Flash data sheet for more details on reading from or writing to the Flash device.) The accesses to the Flash are based on a direct decode of CPU accesses to a memory window defined in either the 82559ER Flash Base Address Register (PCI Configuration space at offset 18H) or the Expansion ROM Base Address Register (PCI Configuration space at offset 30H). The 82559ER asserts control to the Flash when it decodes a valid access.
The 82559ER supports an external Flash memory (or boot PROM) of up to 128 Kbyte. The Expansion ROM BAR can be separately disabled by setting the corresponding bit in the EEPROM, word AH.
Note: Flash accesses must always be assembled or disassembled by the 82559ER whenever the access is greater than a
The serial EEPROM stores configuration data for the 82559ER and is a serial in/serial out device. The 82559ER supports a either a 64 register or 256 register size EEPROM and automatically detects the EEPROM’s size. The EEPROM should operate at a frequency of at least 1 MHz.
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