CSR I/O Read Cycle | Intel GD82559ER instruction

Networking Silicon — GD82559ER

The figures below show CSR zero wait-state I/O read and write cycles. In the case of accessing the Control/Status Registers, the CPU is the initiator and the 82559ER is the target of the transaction.

SYSTEM

CLK

			1								2								3				4				5					6		7						8									9
FRAME#
FRAME#

AD

								ADDR													DATA
								ADDR													DATA
C/BE#

							I/O RD												BE#
							I/O RD												BE#

IRDY#

82559ER

TRDY#

DEVSEL#

STOP#

Figure 2. CSR I/O Read Cycle

Read Accesses: The CPU, as the initiator, drives address lines AD[31:0], the command and byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. As a slave, the 82559ER controls the TRDY# signal and provides valid data on each data access. The 82559ER allows the CPU to issue only one read cycle when it accesses the Control/Status Registers, generating a disconnect by asserting the STOP# signal. The CPU can insert wait states by de-asserting IRDY# when it is not ready.

SYSTEM

CLK

			1								2						3		4				5					6		7						8								9
FRAME#
FRAME#

AD

								ADDR									DATA
								ADDR									DATA
C/BE#

							I/O WR										BE#
							I/O WR										BE#

IRDY#

82559ER

TRDY#

DEVSEL#

STOP#

Figure 3. CSR I/O Write Cycle

Write Accesses: The CPU, as the initiator, drives the address lines AD[31:0], the command and byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. It also provides the 82559ER with valid data on each data access immediately after asserting IRDY#. The 82559ER

Datasheet

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Intel GD82559ER manual CSR I/O Read Cycle

GD82559ER specifications

The Intel GD82559ER is a highly regarded network interface controller (NIC) designed for use in various computing environments, primarily for stable connectivity in both desktop and server applications. Released as part of the 82559 family of Ethernet controllers, the GD82559ER features advanced technologies that enhance performance, reliability, and manageability.

One of the standout features of the 82559ER is its ability to support both 10/100 Mbps Ethernet. This dual capability allows the controller to operate in a wide range of network settings, making it adaptable to legacy systems while also providing support for modern Ethernet standards. This versatility is crucial for organizations looking to maintain operational effectiveness without the need for immediate upgrades to their existing infrastructure.

The GD82559ER employs a PCI interface, which allows it to connect with various devices and motherboards easily, making it a go-to choice for manufacturers aiming for integration in their systems. It also includes features like Auto-Negotiation, enabling the NIC to automatically detect and select the appropriate speed and duplex mode for optimal performance. This capability is essential in dynamic networking environments, where devices from various generations coexist.

Power management is another critical aspect of the GD82559ER. The controller supports advanced power-saving features like PCI Power Management, reducing energy consumption during low-usage periods. This not only contributes to lower operational costs but also aligns with modern eco-friendly initiatives in technology.

Additionally, the GD82559ER comes equipped with advanced diagnostics and monitoring capabilities. This enhances the network's manageability by allowing administrators to track performance metrics and diagnose issues effectively. Through its onboard diagnostics, the controller aids in ensuring a stable network connection, allowing for timely interventions when issues arise.

The controller is also designed with a robust architecture that supports various operating systems, facilitating a broad implementation across different platforms. As a result, the GD82559ER has become a reliable option for system builders and enterprises focused on building dependable networking solutions.

Overall, the Intel GD82559ER is a versatile, high-performance network interface controller that continues to serve as a foundational component for computer systems that require efficient, reliable networking capabilities. Its combination of technologies and features makes it a popular choice in diverse computing environments.

Contents

GD82559ER Fast Ethernet PCI Controller Product Features Mar First release Revision Description Contents PCI Configuration Registers Electrical and Timing Specifications GD82559ER Networking Silicon Datasheet Introduction GD82559ER OverviewSuggested Reading GD82559ER Networkin g Silicon Datasheet Parallel Subsystem Overview GD82559ER Architectural Overview GD82559ER Networkin g Silicon Fifo Subsystem Overview 10/100 Mbps Physical Layer Unit 10/100 Mbps Serial CSMA/CD Unit Overview GD82559ER Networkin g Silicon Datasheet Signal Type Definitions Signal DescriptionsPCI Bus Interface Signals Address and Data Signals Interface Control Signals System and Power Management Signals Local Memory Interface Signals Testability Port Signals PHY Signals GD82559ER Networkin g Silicon Datasheet 82559ER Initialization GD82559ER Media Access Control Functional DescriptionInitialization Effects on 82559ER Units D3 to D0 Software Selective PCI Interface Control/Status Register CSR Accesses1 82559ER Bus Operations 1.1 82559ER Bus Slave Operation CSR I/O Read Cycle Flash Buffer Read Cycle Flash Buffer Accesses Flash Buffer Write Cycle Retry Premature Accesses 1.2 82559ER Bus Master Operation Error Handling Memory Read Burst Cycle Memory Write and Invalidate Read Align Power Management Event Signal Clockrun Signal 4.1 D0 Power State Power States4.2 D1 Power State 4.3 D2 Power State Understanding Power Requirements 4.4 D3 Power StatePower State Conditions 100 Mbs 10 Mbs PCI CLK Alternate Reset Signal Auxiliary Power SignalIsolate Signal Power State Link 82559ER Functionality Isolate Signal Behavior to PCI Power Good Signal PCI Reset Signal Interestin g Packet Events Wake-up Events Parallel Flash Interface Serial Eeprom InterfaceLink Status Change Event Subsystem ID Word IA Byte Eeprom Words Field Descriptions 10/100 Mbps CSMA/CD UnitBits Name Description ALL Flow Control Full DuplexAddress Filtering Modifications Long Frame Reception Media Independent Interface MII Management Interface GD82559ER Test Port Functionality Asynchronous Test ModeIntroduction Test Function Description Nand Tree TriStateNand Tree Chains Chain Order FLD6 STOP# FLD2 GNT# FLD3 PERR# FLD4 PAR FLD5FLD7 AD9 GD82559ER Networkin g Silicon Datasheet 100BASE-TX PHY Unit GD82559ER Physical Layer Functional Description1 100BASE-TX Transmit Clock Generation 2 100BASE-TX Transmit Blocks Invalid 2.2 100BASE-TX Scrambler and MLT-3 Encoder Transmit Driver 2.3 100BASE-TX Transmit FramingMagnetics Modules Vendor Model/Type 3 100BASE-TX Receive Blocks 10BASE-T Functionality 5 100BASE-TX Link Integrity and Auto-Negotiation Solution4 100BASE-TX Collision Detection Auto 10/100 Mbps Speed Selection 3 10BASE-T Receive Blocks 2 10BASE-T Transmit Blocks2.1 10BASE-T Manchester Encoder 2.2 10BASE-T Driver and Filter 4 10BASE-T Collision Detection Auto-Negotiation Functionality5 10BASE-T Link Integrity 6 10BASE-T Jabber Control Function Parallel Detect and Auto-Negotiation Description Auto-Negotiation and Parallel Detect LED Description Liled T L E D Two and Three LED Schematic Diagram PCI Configuration Registers LAN Ethernet PCI Configuration SpacePCI Vendor ID and Device ID Registers PCI Command Register PCI Command Register Bits PCI Command Register PCI Status Register PCI Status Register Bits PCI Status Register PCI Revision ID Register PCI Class Code RegisterPCI Cache Line Size Register PCI Latency Timer PCI Header TypePCI Base Address Registers CSR I/O Mapped Base Address Register CSR Memory Mapped Base Address RegisterFlash Memory Mapped Base Address Register Expansion ROM Base Address Register Capability Pointer PCI Subsystem Vendor ID and Subsystem ID RegistersInterrupt Line Register ER ID Fields Programming Interrupt Pin Register Power Management Capabilities RegisterMinimum Grant Register Maximum Latency Register Power Management Control and Status Register Power Management Control/Status Register Pmcsr Data Register Ethernet Data RegisterData Select Data Scale Data Reported LAN Ethernet Control/Status Registers Control/Status RegistersD31 D16 D15 Lower Word Offset System Control Block Status Word System Control Block General Pointer System Control Block Command WordPort Flash Control Register Power Management Driver Register Receive Direct Memory Access Byte CountPower Management Driver Register Early Receive Interrupt General Status Register General Control RegisterGeneral Control Register General Status Register Statistical Counters ER Statistical CountersCounter Description Frame indicator, they are not counted GD82559ER Networking Silicon Datasheet PHY Unit Registers Bits Name Description DefaultMDI Registers 0 Register 0 Control Register Bit Definitions Register 1 Status Register Bit Definitions Register 2 PHY Identifier Register Bit Definitions Bits Name Description Default 150Register 3 PHY Identifier Register Bit Definitions Value 0154H MDI Register 16 MDI Registers 8100BASE-TX 10BASE-T Register 17 PHY Unit Special Control Bit Definitions Register 22 Receive Symbol Error Counter Bit Definitions Register 18 PHY Address RegisterBits Counter Bit Definitions Register 23 100BASE-TX Receive Premature End of Frame ErrorRegister 26 Equalizer Control and Status Bit Definitions Register 27 PHY Unit Special Control Bit Definitions GD82559ER Networking Silicon Datasheet DC Specifications Electrical and Timing SpecificationsGeneral DC Specifications PCI Interface DC Specifications Flash/EEPROM Interface DC Specifications LED Voltage/Current CharacteristicsBASE-TX Voltage/Current Characteristics BASE-T Voltage/Current Characteristics Symbol ParameterVCC/2 AC Specifications for PCI Signaling AC Specifications Clocks Specifications Timing SpecificationsPCI Clock Specifications 10.4.1.2 X1 Specifications Symbol PCI Level Units Timing ParametersMeasurement and Test Conditions PCI Timings Symbol Parameter Min Max UnitsFlash Interface Timings PCI Timing Parameters Flash Timing Parameters Eeprom Timing Parameters Eeprom Interface Timings Symbol Parameter Min Typ Max Symbol Parameter Condition Min Typ Max UnitsPHY Timings BASE-T NLP Timing Parameters TDP/TDN Differential HLS Data 1400 Output Peak Jitter Symbol Parameter Condition Min Typ Max Units T64 GD82559ER Networking Silicon Datasheet Package Information Package and Pinout Information 12.2.1 GD82559ER Pin Assignments Pinout InformationGD82559ER Pin Assignments Pin Name PERR# GNT# VCC STOP# INTA# DEVSEL# VCC VSSFLA1 FLA0 GD82559ER Ball Grid Array Diagram 12.2.2 GD82559ER Ball Grid Array Diagram