Intel GD82559ER manual Read Align

Networking Silicon — GD82559ER

1.Minimum transfer of one cache line

2.Active byte enable bits (or BE#[3:0] are all low) during MWI access

3.The 82559ER may cross the cache line boundary only if it intends to transfer the next cache line too.

To ensure the above conditions, the 82559ER may use the MWI command only if the following conditions hold:

1.The Cache Line Size (CLS) written in the CLS register during PCI configuration is 8 or 16 Dwords.

2.The accessed address is cache line aligned.

3.The 82559ER has at least 8 or 16 Dwords of data in its receive FIFO.

4.There are at least 8 or 16 Dwords of data space left in the system memory buffer.

5.The MWI Enable bit in the PCI Configuration Command register, bit 4, should is set to 1b.

6.The MWI Enable bit in the 82559ER Configure command should is set to 1b. (Details on the Configure command are described in the Software Developer’s Manual.)

If any one of the above conditions does not hold, the 82559ER will use the MW command. If a MWI cycle has started and one of the conditions is no longer valid (for example, the data space in the memory buffer is now less than CLS), then the 82559ER terminates the MWI cycle at the end of the cache line. The next cycle will be either a MW or MWI cycle depending on the conditions listed above.

If the 82559ER started a MW cycle and reached a cache line boundary, it either continues or terminates the cycle depending on the Terminate Write on Cache Line configuration bit of the 82559ER Configure command (byte 3, bit 3). If this bit is set, the 82559ER terminates the MW cycle and attempts to start a new cycle. The new cycle is a MWI cycle if this bit is set and all of the above listed conditions are met. If the bit is not set, the 82559ER continues the MW cycle across the cache line boundary if required. (Details on the Configure command are described in the Software Developer’s Manual .)

4.2.1.2.2Read Align

The Read Align feature enhances the 82559ER’s performance in cache line oriented systems. In these particular systems, starting a PCI transaction on a non-cache line aligned address may cause low performance.

To resolve this performance anomaly, the 82559ER attempts to terminate transmit DMA cycles on a cache line boundary and start the next transaction on a cache line aligned address. This feature is enabled when the Read Align Enable bit is set in the 82559ER Configure command (byte 3, bit 2). (Details on the Configure command are described in the Software Developer’s Manual .)

If this bit is set, the 82559ER operates as follows:

•When the 82559ER is almost out of resources on the transmit DMA (that is, the transmit FIFO is almost full), it attempts to terminate the read transaction on the nearest cache line boundary when possible.

•When the arbitration counter’s feature is enabled (in other words, the Transmit DMA Maximum Byte Count value is set in the Configure command), the 82559ER switches to other pending DMAs on the cache line boundary only.

Note the following:

Datasheet 21