Intel GD82559ER manual PCI Subsystem Vendor ID and Subsystem ID Registers, Capability Pointer

Networking Silicon — GD82559ER

7.1.10PCI Subsystem Vendor ID and Subsystem ID Registers

The Subsystem Vendor ID field identifies the vendor of an 82559ER-based solution. The Subsystem Vendor ID values are based upon the vendor’s PCI Vendor ID and is controlled by the PCI Special Interest Group (SIG).

The Subsystem ID field identifies the 82559ER-based specific solution implemented by the vendor indicated in the Subsystem Vendor ID field.

The 82559ER provides support for configurable Subsystem Vendor ID and Subsystem ID fields. After hardware reset is de-asserted, the 82559ER automatically reads addresses Ah through Ch of the EEPROM. The first of these 16-bit values is used for controlling various 82559ER functions. The second is the Subsystem ID value, and the third is the Subsystem Vendor ID value. Again, the default values for the Subsystem ID and Subsystem Vendor ID are 0h and 0H, respectively.

The 82559ER checks bit numbers 15, 14, and 13 in the EEPROM, word Ah and functions according to Table 7 below.

Table 7. 82559ER ID Fields Programming

Bits 15, 14	Bit 13	Device ID	Vendor ID	Revision ID	Subsystem ID	Subsystem
						Vendor ID
11b, 10b,	X	1209H	8086H	09H	0000H	0000H
00b					(Default)	(Default)
01b	0b	1209H	8086H	09H	Word BH	Word CH
01b	1b	1209H	8086H	Word AH,	Word BH	Word CH
				bits 10:8

Note: The Revision ID is subject to change according to the silicon stepping.

The above table implies that if the 82559ER detects the presence of an EEPROM (as indicated by a value of 01b in bits 15 and 14), then bit number 13 determines whether the values read from the EEPROM, words Bh and CH, will be loaded into the Subsystem ID (word BH) and Subsystem Vendor ID (word CH) fields. If bits 15 and 14 equal 01b and bit 13 equals 1b, the three least significant bits of the Revision ID field are programmed by bits 8-10 of the first EEPROM word, word AH.

Between the de-assertion of reset and the completion of the automatic EEPROM read, the 82559ER does not respond to any PCI configuration cycles. If the 82559ER happens to be accessed during this time, it will Retry the access. More information on Retry is provided in Section 4.2.1.1.3, “Retry Premature Accesses” on page 17 .

7.1.11Capability Pointer

The Capability Pointer is a hard coded byte register with a value of DCH. It provides an offset within the Configuration Space for the location of the Power Management registers.

7.1.12Interrupt Line Register

The Interrupt Line register identifies which system interrupt request line on the interrupt contoller the device’s PCI interrupt request pin (as defined in the Interrupt Pin register) is routed to.

Datasheet 53