Receive Direct Memory Access Byte Count | Intel GD82559ER instruction

GD82559ER — Networking Silicon

	Bits	Description


	29	Interrupt Enable. When this bit is set to 1b by software, the 82559ER asserts an interrupt to
	29	indicate the end of an MDI cycle.
		indicate the end of an MDI cycle.

	28	Ready. This bit is set to 1b by the 82559ER at the end of an MDI transaction. It should be
	28	reset to 0b by software at the same time the command is written.


	27:26	Opcode. These bits define the opcode: 01 for MDI write and 10 for MDI read. All other values
	27:26	(00 and 11) are reserved.
		(00 and 11) are reserved.

	25:21	PHY Address. This field of bits contains the PHY address (Default = 00001b).

	20:16	PHY Register Address. This field of bits contains the address of the PHY Register to be
	20:16	accessed.
		accessed.

		Data. In a write command, software places the data bits in this field, and the 82559ER
	15:0	transfers the data to the PHY unit. During a read command, the 82559ER reads these bits
	15:0	serially from the PHY register (specified by bits 20:16), and software reads the data from this

		location.

8.1.8Receive Direct Memory Access Byte Count

The Receive DMA Byte Count register keeps track of how many bytes of receive data have been passed into host memory via DMA.

8.1.9Early Receive Interrupt

The Early Receive Interrupt register allows the 82559ER to generate an early interrupt depending on the length of the frame. An early interrupt is indicated by the ER bit in the SCB Status Word and the assertion of the INTA# signal.

8.1.10Flow Control Register

The Flow Control Register contains the following fields:

•Flow Control Command

The Flow Control Command field describes the action of the flow control process (for example, pause, on, or off).

•Flow Control Threshold

The Flow Control Threshold field contains the threshold value (in other words, the number of free bytes in the Receive FIFO).

8.1.11Power Management Driver Register

The 82559ER provides an indication in memory and I/O space that a wake-up event has occurred. It is located in the PMDR.

Table 11. Power Management Driver Register

Bits	Default	Read/Write	Description


31	0b	Read/Clear	Link Status Change Indication. The link status change bit is set
			following a change in link status and is cleared by writing a 1b to it.

30	0b	Read	Not Supported, will always read as a ‘0’.

Datasheet

GD82559ER specifications

The Intel GD82559ER is a highly regarded network interface controller (NIC) designed for use in various computing environments, primarily for stable connectivity in both desktop and server applications. Released as part of the 82559 family of Ethernet controllers, the GD82559ER features advanced technologies that enhance performance, reliability, and manageability.

One of the standout features of the 82559ER is its ability to support both 10/100 Mbps Ethernet. This dual capability allows the controller to operate in a wide range of network settings, making it adaptable to legacy systems while also providing support for modern Ethernet standards. This versatility is crucial for organizations looking to maintain operational effectiveness without the need for immediate upgrades to their existing infrastructure.

The GD82559ER employs a PCI interface, which allows it to connect with various devices and motherboards easily, making it a go-to choice for manufacturers aiming for integration in their systems. It also includes features like Auto-Negotiation, enabling the NIC to automatically detect and select the appropriate speed and duplex mode for optimal performance. This capability is essential in dynamic networking environments, where devices from various generations coexist.

Power management is another critical aspect of the GD82559ER. The controller supports advanced power-saving features like PCI Power Management, reducing energy consumption during low-usage periods. This not only contributes to lower operational costs but also aligns with modern eco-friendly initiatives in technology.

Additionally, the GD82559ER comes equipped with advanced diagnostics and monitoring capabilities. This enhances the network's manageability by allowing administrators to track performance metrics and diagnose issues effectively. Through its onboard diagnostics, the controller aids in ensuring a stable network connection, allowing for timely interventions when issues arise.

The controller is also designed with a robust architecture that supports various operating systems, facilitating a broad implementation across different platforms. As a result, the GD82559ER has become a reliable option for system builders and enterprises focused on building dependable networking solutions.

Overall, the Intel GD82559ER is a versatile, high-performance network interface controller that continues to serve as a foundational component for computer systems that require efficient, reliable networking capabilities. Its combination of technologies and features makes it a popular choice in diverse computing environments.

Intel GD82559ER manual Receive Direct Memory Access Byte Count, Early Receive Interrupt

Models: GD82559ER